VLSI realization of low complexity pipelined LMS filter using distributed arithmetic

This paper presents a new low complexity architecture of least-mean-square (LMS) adaptive filter using distributed arithmetic (DA). The DA based LMS adaptive filter requires lookup tables (LUTs) for filtering and weight updating operation whose complexities grow exponential with filter order. In the proposed technique, the complexity of LUT for DA based LMS adaptive filter is reduced by two new serial implementations. These are based on AND cells (structure-I) and 2-to-1 multiplexer cells (structure-II) followed by an adder tree. Both the structures have reduced the hardware complexity of proposed filter significantly. Compared with the best existing scheme, the proposed designs guarantee to have smaller area and lower power. From synthesis results, it is found that the proposed structure-I for 16^th order occupies 53.57 % less area and consumes 55.06 % less power; utilizes 48.5 % and 67.24 % less number of LUT and FF respectively while the structure-II for 16^th order occupies 52.14 % less area and consumes 53.69 % less power; utilizes 47.5 % and 65.51 % less number of LUT and FF respectively, as compared to the best existing design.