VLSI implementation of throughput efficient distributed arithmetic based LMS adaptive filter

Mohd Tasleem Khan; Shaik Rafi Ahamed

doi:10.1007/978-981-10-7470-7_3

VLSI implementation of throughput efficient distributed arithmetic based LMS adaptive filter

Mohd Tasleem Khan^*
, Shaik Rafi Ahamed

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

3 Citations (Scopus)

Abstract

A new throughput efficient implementation scheme for least mean square (LMS) adaptive filter using distributed arithmetic (DA) is presented for IEEE 802.11b PHY scenarios. It is based on pre-computing and storing the filter partial products in lookup tables (LUTs). In contrast to fixed coefficients filter, an adaptive filter requires each stored partial product to be updated time-to-time. This paper presents a new strategy for DA based adaptive filter using offset binary coding (OBC) technique. The proposed strategy eliminates two oldest sample and allows possible decomposition of LUT into four sub-LUTs. Hence, the proposed approach provides significant improvement in throughput at the cost of few 2-to-1 multiplexers. Synthesis results have shown that the proposed scheme occupies almost similar area and improves the throughput by several fold. For instance, a 32- tap adaptive filter with the proposed implementation produces nearly 1.8 MSPS (million samples per second) more throughput as compared to the best existing scheme.

Original language	English
Title of host publication	VLSI Design and Test
Subtitle of host publication	21st International Symposium, VDAT 2017, Roorkee, India, June 29 – July 2, 2017, Revised Selected Papers
Editors	Brajesh Kumar Kaushik, Sudeb Dasgupta, Virendra Singh
Publisher	Springer
Pages	24-35
Number of pages	12
Volume	711
ISBN (Electronic)	978-981-10-7470-7
ISBN (Print)	978-981-10-7469-1
DOIs	https://doi.org/10.1007/978-981-10-7470-7_3
Publication status	Published - 21 Dec 2017
Event	21st International Symposium on VLSI Design and Test 2017 - Roorkee, India Duration: 29 Jun 2017 → 2 Jul 2017

Publication series

Name	Communications in Computer and Information Science
Volume	711
ISSN (Print)	1865-0929

Conference

Conference	21st International Symposium on VLSI Design and Test 2017
Abbreviated title	VDAT 2017
Country/Territory	India
City	Roorkee
Period	29/06/17 → 2/07/17

Keywords

Distributed arithmetic (DA)
Finite impulse response (FIR) filter
Least mean square (LMS)
Look-up table (LUT)

ASJC Scopus subject areas

General Computer Science
General Mathematics

Access to Document

10.1007/978-981-10-7470-7_3

Cite this

Khan, M. T., & Ahamed, S. R. (2017). VLSI implementation of throughput efficient distributed arithmetic based LMS adaptive filter. In B. K. Kaushik, S. Dasgupta, & V. Singh (Eds.), VLSI Design and Test: 21st International Symposium, VDAT 2017, Roorkee, India, June 29 – July 2, 2017, Revised Selected Papers (Vol. 711, pp. 24-35). (Communications in Computer and Information Science; Vol. 711). Springer. https://doi.org/10.1007/978-981-10-7470-7_3

Khan, Mohd Tasleem ; Ahamed, Shaik Rafi. / VLSI implementation of throughput efficient distributed arithmetic based LMS adaptive filter. VLSI Design and Test: 21st International Symposium, VDAT 2017, Roorkee, India, June 29 – July 2, 2017, Revised Selected Papers. editor / Brajesh Kumar Kaushik ; Sudeb Dasgupta ; Virendra Singh. Vol. 711 Springer, 2017. pp. 24-35 (Communications in Computer and Information Science).

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abstract = "A new throughput efficient implementation scheme for least mean square (LMS) adaptive filter using distributed arithmetic (DA) is presented for IEEE 802.11b PHY scenarios. It is based on pre-computing and storing the filter partial products in lookup tables (LUTs). In contrast to fixed coefficients filter, an adaptive filter requires each stored partial product to be updated time-to-time. This paper presents a new strategy for DA based adaptive filter using offset binary coding (OBC) technique. The proposed strategy eliminates two oldest sample and allows possible decomposition of LUT into four sub-LUTs. Hence, the proposed approach provides significant improvement in throughput at the cost of few 2-to-1 multiplexers. Synthesis results have shown that the proposed scheme occupies almost similar area and improves the throughput by several fold. For instance, a 32- tap adaptive filter with the proposed implementation produces nearly 1.8 MSPS (million samples per second) more throughput as compared to the best existing scheme.",

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Khan, MT & Ahamed, SR 2017, VLSI implementation of throughput efficient distributed arithmetic based LMS adaptive filter. in BK Kaushik, S Dasgupta & V Singh (eds), VLSI Design and Test: 21st International Symposium, VDAT 2017, Roorkee, India, June 29 – July 2, 2017, Revised Selected Papers. vol. 711, Communications in Computer and Information Science, vol. 711, Springer, pp. 24-35, 21st International Symposium on VLSI Design and Test 2017, Roorkee, India, 29/06/17. https://doi.org/10.1007/978-981-10-7470-7_3

VLSI implementation of throughput efficient distributed arithmetic based LMS adaptive filter. / Khan, Mohd Tasleem; Ahamed, Shaik Rafi.
VLSI Design and Test: 21st International Symposium, VDAT 2017, Roorkee, India, June 29 – July 2, 2017, Revised Selected Papers. ed. / Brajesh Kumar Kaushik; Sudeb Dasgupta; Virendra Singh. Vol. 711 Springer, 2017. p. 24-35 (Communications in Computer and Information Science; Vol. 711).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

TY - GEN

T1 - VLSI implementation of throughput efficient distributed arithmetic based LMS adaptive filter

AU - Khan, Mohd Tasleem

AU - Ahamed, Shaik Rafi

N1 - Publisher Copyright: © Springer Nature Singapore Pte Ltd 2017.

PY - 2017/12/21

Y1 - 2017/12/21

N2 - A new throughput efficient implementation scheme for least mean square (LMS) adaptive filter using distributed arithmetic (DA) is presented for IEEE 802.11b PHY scenarios. It is based on pre-computing and storing the filter partial products in lookup tables (LUTs). In contrast to fixed coefficients filter, an adaptive filter requires each stored partial product to be updated time-to-time. This paper presents a new strategy for DA based adaptive filter using offset binary coding (OBC) technique. The proposed strategy eliminates two oldest sample and allows possible decomposition of LUT into four sub-LUTs. Hence, the proposed approach provides significant improvement in throughput at the cost of few 2-to-1 multiplexers. Synthesis results have shown that the proposed scheme occupies almost similar area and improves the throughput by several fold. For instance, a 32- tap adaptive filter with the proposed implementation produces nearly 1.8 MSPS (million samples per second) more throughput as compared to the best existing scheme.

AB - A new throughput efficient implementation scheme for least mean square (LMS) adaptive filter using distributed arithmetic (DA) is presented for IEEE 802.11b PHY scenarios. It is based on pre-computing and storing the filter partial products in lookup tables (LUTs). In contrast to fixed coefficients filter, an adaptive filter requires each stored partial product to be updated time-to-time. This paper presents a new strategy for DA based adaptive filter using offset binary coding (OBC) technique. The proposed strategy eliminates two oldest sample and allows possible decomposition of LUT into four sub-LUTs. Hence, the proposed approach provides significant improvement in throughput at the cost of few 2-to-1 multiplexers. Synthesis results have shown that the proposed scheme occupies almost similar area and improves the throughput by several fold. For instance, a 32- tap adaptive filter with the proposed implementation produces nearly 1.8 MSPS (million samples per second) more throughput as compared to the best existing scheme.

KW - Distributed arithmetic (DA)

KW - Finite impulse response (FIR) filter

KW - Least mean square (LMS)

KW - Look-up table (LUT)

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BT - VLSI Design and Test

A2 - Kaushik, Brajesh Kumar

A2 - Dasgupta, Sudeb

A2 - Singh, Virendra

PB - Springer

T2 - 21st International Symposium on VLSI Design and Test 2017

Y2 - 29 June 2017 through 2 July 2017

ER -

Khan MT, Ahamed SR. VLSI implementation of throughput efficient distributed arithmetic based LMS adaptive filter. In Kaushik BK, Dasgupta S, Singh V, editors, VLSI Design and Test: 21st International Symposium, VDAT 2017, Roorkee, India, June 29 – July 2, 2017, Revised Selected Papers. Vol. 711. Springer. 2017. p. 24-35. (Communications in Computer and Information Science). doi: 10.1007/978-981-10-7470-7_3

VLSI implementation of throughput efficient distributed arithmetic based LMS adaptive filter

Abstract

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Keywords

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