VHDL modelling of the open short tester

Wai Leong Pang; Kok Wai Chew; Florence Chiao Mei Choong; C. L. Chan

VHDL modelling of the open short tester

Wai Leong Pang, Kok Wai Chew, Florence Chiao Mei Choong, C. L. Chan

School of Engineering & Physical Sciences

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

IC (Integrated Circuitry) testing requires the very advanced and sophisticated Advance Test Equipment (ATE) that costs multi million USD. The cost of IC testing is increasing yearly and it will exceed the cost of manufacturing in future. The manufacturers are interested to lower down the manufacturing cost. Low cost tester is one of the options to reduce the manufacturing cost. The low cost FPGA realization of Open/Short Test on IC is introduced to reduce the IC test cost. The open short test is selected, because it is the first IC test. The Very High Speed Integrated Circuit Hardware Description Language (VHDL) is used to model the Open/Short Test on IC and the design is capable to perform the open/short test.

Original language	English
Title of host publication	Proceedings of the 6th WSEAS International Conference on Instrumentation, Measurement, Circuits and Systems
Pages	34-38
Publication status	Published - 15 Apr 2007
Event	6th WSEAS International Conference on Instrumentation, Measurement, Circuits and Systems - Hangzhou, China Duration: 15 Apr 2007 → 17 Apr 2007

Conference

Conference	6th WSEAS International Conference on Instrumentation, Measurement, Circuits and Systems
Abbreviated title	IMCAS 2007
Country/Territory	China
City	Hangzhou
Period	15/04/07 → 17/04/07

Keywords

VHDL modelling
open short test
IC tester

Access to Document

https://dl.acm.org/doi/10.5555/1364520.1364527

Cite this

@inproceedings{f38d9f4c0e1a4a2c9199353744bd23e7,

title = "VHDL modelling of the open short tester",

abstract = "IC (Integrated Circuitry) testing requires the very advanced and sophisticated Advance Test Equipment (ATE) that costs multi million USD. The cost of IC testing is increasing yearly and it will exceed the cost of manufacturing in future. The manufacturers are interested to lower down the manufacturing cost. Low cost tester is one of the options to reduce the manufacturing cost. The low cost FPGA realization of Open/Short Test on IC is introduced to reduce the IC test cost. The open short test is selected, because it is the first IC test. The Very High Speed Integrated Circuit Hardware Description Language (VHDL) is used to model the Open/Short Test on IC and the design is capable to perform the open/short test.",

keywords = "VHDL modelling, open short test, IC tester",

author = "Pang, {Wai Leong} and Chew, {Kok Wai} and Choong, {Florence Chiao Mei} and Chan, {C. L.}",

year = "2007",

month = apr,

day = "15",

language = "English",

pages = "34--38",

booktitle = "Proceedings of the 6th WSEAS International Conference on Instrumentation, Measurement, Circuits and Systems",

note = "6th WSEAS International Conference on Instrumentation, Measurement, Circuits and Systems, IMCAS 2007 ; Conference date: 15-04-2007 Through 17-04-2007",

}

Pang, WL, Chew, KW, Choong, FCM & Chan, CL 2007, VHDL modelling of the open short tester. in Proceedings of the 6th WSEAS International Conference on Instrumentation, Measurement, Circuits and Systems. pp. 34-38, 6th WSEAS International Conference on Instrumentation, Measurement, Circuits and Systems, Hangzhou, China, 15/04/07. <https://dl.acm.org/doi/10.5555/1364520.1364527>

TY - GEN

T1 - VHDL modelling of the open short tester

AU - Pang, Wai Leong

AU - Chew, Kok Wai

AU - Choong, Florence Chiao Mei

AU - Chan, C. L.

PY - 2007/4/15

Y1 - 2007/4/15

N2 - IC (Integrated Circuitry) testing requires the very advanced and sophisticated Advance Test Equipment (ATE) that costs multi million USD. The cost of IC testing is increasing yearly and it will exceed the cost of manufacturing in future. The manufacturers are interested to lower down the manufacturing cost. Low cost tester is one of the options to reduce the manufacturing cost. The low cost FPGA realization of Open/Short Test on IC is introduced to reduce the IC test cost. The open short test is selected, because it is the first IC test. The Very High Speed Integrated Circuit Hardware Description Language (VHDL) is used to model the Open/Short Test on IC and the design is capable to perform the open/short test.

AB - IC (Integrated Circuitry) testing requires the very advanced and sophisticated Advance Test Equipment (ATE) that costs multi million USD. The cost of IC testing is increasing yearly and it will exceed the cost of manufacturing in future. The manufacturers are interested to lower down the manufacturing cost. Low cost tester is one of the options to reduce the manufacturing cost. The low cost FPGA realization of Open/Short Test on IC is introduced to reduce the IC test cost. The open short test is selected, because it is the first IC test. The Very High Speed Integrated Circuit Hardware Description Language (VHDL) is used to model the Open/Short Test on IC and the design is capable to perform the open/short test.

KW - VHDL modelling

KW - open short test

KW - IC tester

M3 - Conference contribution

SP - 34

EP - 38

BT - Proceedings of the 6th WSEAS International Conference on Instrumentation, Measurement, Circuits and Systems

T2 - 6th WSEAS International Conference on Instrumentation, Measurement, Circuits and Systems

Y2 - 15 April 2007 through 17 April 2007

ER -

VHDL modelling of the open short tester

Abstract

Conference

Keywords

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