This paper describes the principles and operation of two new PWM generation techniques. To provide an acceptable quality modulated output, the reference look-up table is retained, while emphasis is put on alternative modulation strategies. In the first design, the voltage variation is performed with the aid of two cascaded rate multipliers, providing implicit frequency multiplication. The alternative design takes advantage of two cascaded counters providing implicit period multiplication. The design is tailored towards silicon area reduction in an ASIC implementation. As a proving stage the two designs are implemented using XILINX programmable logic cell arrays.
|Number of pages||6|
|Journal||IEE Conference Publication|
|Publication status||Published - 1990|
|Event||Fourth International Conference on Power Electronics and Variable-Speed Drives - London, Engl|
Duration: 17 Jul 1990 → 19 Jul 1990