Towards terabit/s input to silicon VLSI - a demonstrator experiment

The physical limit on electronic data communication rates between silicon chips is projected to be of the order of Tbit/s over cm-scale connections. The semiconductor industry predicts that this level of i/o is likely to be required in the near future. Free-space optical connections to silicon VLSI are potentially able to offer much higher data-rates than electrical interconnects and are promising for future high-performance electronic systems. We have assembled the components of an optoelectronic 15 Gbit/s crossbar switch designed to include, internally, an optical data rate to a hybrid InGaAs/silicon chip in the Tbit/s regime. Input to the demonstrator is by an 8×8 VCSEL array operating at 250 Mbit/s/channel, and these 64 channels are fanned out 8×8 times to give the high data rate onto the hybrid chip. This chip includes an array of 4096 InGaAs-based detectors flip chip bonded to silicon CMOS. The custom-designed CMOS performs packet routing under the control of an optical clock and the routed signals are output via differential modulator pairs, interlaced between the detectors on the InGaAs chip.