Abstract
This paper presents shared-variable synchronization approaches for dataflow programming. The mechanisms do not require any substantial model of computation (MoC) modifi-cation, and is portable across both for hardware (HW) and software (SW) low-level code synthesis. With the shared-variable formalization, the benefits of the dataflow MoC are maintained, however the space and energy efficiency of an application can be significantly improved. The approach targets Dynamic Process Network (DPN) dataflow applications, thus making them also suitable for less expressive models e.g. synchronous and cyclo-static dataflow that DPN subsumes. The approach is validated through the analysis and optimization of a High-Efficiency Video Coding (HEVC) decoder implemented in the RVC-CAL dataflow language targeting a multi-core platform. Experimental results show how, starting from an initial design that does not use the shared-variable formalism, frames per second throughput performance is increased by a factor of 21.
| Original language | English |
|---|---|
| Title of host publication | 2018 IEEE International Workshop on Signal Processing Systems (SiPS) |
| Publisher | IEEE |
| Pages | 263-268 |
| Number of pages | 6 |
| ISBN (Electronic) | 9781538663189 |
| DOIs | |
| Publication status | Published - 3 Jan 2019 |
| Event | 2018 IEEE Workshop on Signal Processing Systems - Cape Town, South Africa Duration: 21 Oct 2018 → 24 Oct 2018 |
Publication series
| Name | IEEE International Workshop on Signal Processing Systems (SiPS) |
|---|---|
| Publisher | IEEE |
| ISSN (Electronic) | 2374-7390 |
Conference
| Conference | 2018 IEEE Workshop on Signal Processing Systems |
|---|---|
| Abbreviated title | SiPS 2018 |
| Country/Territory | South Africa |
| City | Cape Town |
| Period | 21/10/18 → 24/10/18 |
ASJC Scopus subject areas
- Electrical and Electronic Engineering
- Signal Processing
- Applied Mathematics
- Hardware and Architecture
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