Shallow junctions in silicon via low thermal budget processing

B.J. Sealy; A.J. Smith; T. Alzanki; N. Bennett; L. Li; C. Jeynes; B. Colombeau; E.J.H. Collart; N.G. Emerson; R.M. Gwilliam; N.E.B. Cowern

Shallow junctions in silicon via low thermal budget processing

B.J. Sealy, A.J. Smith, T. Alzanki, N. Bennett, L. Li, C. Jeynes, B. Colombeau, E.J.H. Collart, N.G. Emerson, R.M. Gwilliam, N.E.B. Cowern

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

2 Citations (Scopus)

Abstract

The paper summarises recent findings concerning the fabrication of ultra-shallow junctions in silicon for future generations of CMOS devices. In particular we concentrate on vacancy engineering to achieve carrier concentrations of 5-6 × 10²⁰ cm^-3 for boron in silicon without diffusion and report for the first time preliminary data for antimony implants into strained silicon in which even higher carrier concentrations were obtained. All of this can be produced at temperatures below 800°C for annealing times of 10 seconds, without the need for spike annealing, fast ramp rates or laser processing.

Original language	English
Title of host publication	Extended Abstracts of the Sixth International Workshop on Junction Technology, IWJT '06
Pages	10-15
Number of pages	6
Publication status	Published - 2006
Event	6th International Workshop on Junction Technology 2006 - Shanghai, China Duration: 15 May 2006 → 16 May 2006

Conference

Conference	6th International Workshop on Junction Technology 2006
Abbreviated title	IWJT '06
Country/Territory	China
City	Shanghai
Period	15/05/06 → 16/05/06

ASJC Scopus subject areas

Electrical and Electronic Engineering
Electronic, Optical and Magnetic Materials
Atomic and Molecular Physics, and Optics
Surfaces and Interfaces

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Cite this

Sealy, B. J., Smith, A. J., Alzanki, T., Bennett, N., Li, L., Jeynes, C., Colombeau, B., Collart, E. J. H., Emerson, N. G., Gwilliam, R. M., & Cowern, N. E. B. (2006). Shallow junctions in silicon via low thermal budget processing. In Extended Abstracts of the Sixth International Workshop on Junction Technology, IWJT '06 (pp. 10-15). Article 1669437 https://www.scopus.com/inward/record.uri?eid=2-s2.0-34250164621&partnerID=40&md5=725307e499963a00be257c4b6847ff18

@inproceedings{da1ef3e9adb34131a77f3d64b4fd40a6,

title = "Shallow junctions in silicon via low thermal budget processing",

abstract = "The paper summarises recent findings concerning the fabrication of ultra-shallow junctions in silicon for future generations of CMOS devices. In particular we concentrate on vacancy engineering to achieve carrier concentrations of 5-6 × 1020 cm-3 for boron in silicon without diffusion and report for the first time preliminary data for antimony implants into strained silicon in which even higher carrier concentrations were obtained. All of this can be produced at temperatures below 800°C for annealing times of 10 seconds, without the need for spike annealing, fast ramp rates or laser processing.",

author = "B.J. Sealy and A.J. Smith and T. Alzanki and N. Bennett and L. Li and C. Jeynes and B. Colombeau and E.J.H. Collart and N.G. Emerson and R.M. Gwilliam and N.E.B. Cowern",

note = "cited By 2; 6th International Workshop on Junction Technology 2006, IWJT '06 ; Conference date: 15-05-2006 Through 16-05-2006",

year = "2006",

language = "English",

isbn = "1424400473",

pages = "10--15",

booktitle = "Extended Abstracts of the Sixth International Workshop on Junction Technology, IWJT '06",

}

Sealy, BJ, Smith, AJ, Alzanki, T, Bennett, N, Li, L, Jeynes, C, Colombeau, B, Collart, EJH, Emerson, NG, Gwilliam, RM & Cowern, NEB 2006, Shallow junctions in silicon via low thermal budget processing. in Extended Abstracts of the Sixth International Workshop on Junction Technology, IWJT '06., 1669437, pp. 10-15, 6th International Workshop on Junction Technology 2006, Shanghai, China, 15/05/06. <https://www.scopus.com/inward/record.uri?eid=2-s2.0-34250164621&partnerID=40&md5=725307e499963a00be257c4b6847ff18>

TY - GEN

T1 - Shallow junctions in silicon via low thermal budget processing

AU - Sealy, B.J.

AU - Smith, A.J.

AU - Alzanki, T.

AU - Bennett, N.

AU - Li, L.

AU - Jeynes, C.

AU - Colombeau, B.

AU - Collart, E.J.H.

AU - Emerson, N.G.

AU - Gwilliam, R.M.

AU - Cowern, N.E.B.

N1 - cited By 2

PY - 2006

Y1 - 2006

N2 - The paper summarises recent findings concerning the fabrication of ultra-shallow junctions in silicon for future generations of CMOS devices. In particular we concentrate on vacancy engineering to achieve carrier concentrations of 5-6 × 1020 cm-3 for boron in silicon without diffusion and report for the first time preliminary data for antimony implants into strained silicon in which even higher carrier concentrations were obtained. All of this can be produced at temperatures below 800°C for annealing times of 10 seconds, without the need for spike annealing, fast ramp rates or laser processing.

AB - The paper summarises recent findings concerning the fabrication of ultra-shallow junctions in silicon for future generations of CMOS devices. In particular we concentrate on vacancy engineering to achieve carrier concentrations of 5-6 × 1020 cm-3 for boron in silicon without diffusion and report for the first time preliminary data for antimony implants into strained silicon in which even higher carrier concentrations were obtained. All of this can be produced at temperatures below 800°C for annealing times of 10 seconds, without the need for spike annealing, fast ramp rates or laser processing.

UR - http://www.scopus.com/inward/record.url?scp=34250164621&partnerID=8YFLogxK

M3 - Conference contribution

AN - SCOPUS:34250164621

SN - 1424400473

SN - 9781424400478

SP - 10

EP - 15

BT - Extended Abstracts of the Sixth International Workshop on Junction Technology, IWJT '06

T2 - 6th International Workshop on Junction Technology 2006

Y2 - 15 May 2006 through 16 May 2006

ER -

Shallow junctions in silicon via low thermal budget processing

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ASJC Scopus subject areas

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