Shallow junctions in silicon via low thermal budget processing

B.J. Sealy, A.J. Smith, T. Alzanki, N. Bennett, L. Li, C. Jeynes, B. Colombeau, E.J.H. Collart, N.G. Emerson, R.M. Gwilliam, N.E.B. Cowern

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)


The paper summarises recent findings concerning the fabrication of ultra-shallow junctions in silicon for future generations of CMOS devices. In particular we concentrate on vacancy engineering to achieve carrier concentrations of 5-6 × 1020 cm-3 for boron in silicon without diffusion and report for the first time preliminary data for antimony implants into strained silicon in which even higher carrier concentrations were obtained. All of this can be produced at temperatures below 800°C for annealing times of 10 seconds, without the need for spike annealing, fast ramp rates or laser processing.

Original languageEnglish
Title of host publicationExtended Abstracts of the Sixth International Workshop on Junction Technology, IWJT '06
Number of pages6
Publication statusPublished - 2006
Event6th International Workshop on Junction Technology 2006 - Shanghai, China
Duration: 15 May 200616 May 2006


Conference6th International Workshop on Junction Technology 2006
Abbreviated titleIWJT '06

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials
  • Atomic and Molecular Physics, and Optics
  • Surfaces and Interfaces


Dive into the research topics of 'Shallow junctions in silicon via low thermal budget processing'. Together they form a unique fingerprint.

Cite this