Abstract
Field programmable gate arrays (FPGAs) can accelerate image processing by
exploiting fine-grained parallelism opportunities in image operations. FPGA
language designs are often subsets or extensions of existing languages, though
these typically lack suitable hardware computation models so compiling them to
FPGAs leads to inefficient designs. Moreover, these languages lack image
processing domain specificity. Our solution is RIPL, an image processing domain
specific language (DSL) for FPGAs. It has algorithmic skeletons to express
image processing, and these are exploited to generate deep pipelines of highly
concurrent and memory-efficient image processing components.
exploiting fine-grained parallelism opportunities in image operations. FPGA
language designs are often subsets or extensions of existing languages, though
these typically lack suitable hardware computation models so compiling them to
FPGAs leads to inefficient designs. Moreover, these languages lack image
processing domain specificity. Our solution is RIPL, an image processing domain
specific language (DSL) for FPGAs. It has algorithmic skeletons to express
image processing, and these are exploited to generate deep pipelines of highly
concurrent and memory-efficient image processing components.
| Original language | English |
|---|---|
| Title of host publication | Proceedings of the Second International Workshop on FPGAs for Software Programmers |
| Place of Publication | London |
| Pages | 80-81 |
| Number of pages | 2 |
| Publication status | Published - 2015 |