RIPL: A Parallel Image Processing Language for FPGAs

Robert Stewart, Kirsty Duncan, Paulo Garcia, Gregory John Michaelson, Deepayan Bhowmik, Andrew Michael Wallace

Research output: Contribution to journalArticlepeer-review

15 Citations (Scopus)
227 Downloads (Pure)


Specialised FPGA implementations can deliver higher performance and greater power efficiency than embedded CPU or GPU implementations for real time image processing. Programming challenges limit their wider use, because the implementation of FPGA architectures at the Register Transfer Level is time consuming and error prone. Existing software languages supported by High Level Synthesis, whilst providing a productivity improvement, are too general purpose to generate efficient hardware without the use of hardware specific code optimisations. Such optimisations leak hardware details into the abstractions that software languages are there to provide, and they require knowledge of FPGAs to generate efficient hardware e.g. by using language pragmas to partition data structures across memory blocks.

This paper presents a thorough account of RIPL (the Rathlin Image Processing Language), a high level image processing Domain Specific Language for FPGAs. We motivate its design, based on higher order algorithmic skeletons, with requirements from the image processing domain. RIPL’s skeletons suffice to elegantly describe image processing stencils, as well as recursive algorithms with non-local random access patterns. At its core, RIPL employs a dataflow intermediate representation. We give a formal account of the compilation scheme from RIPL skeletons to static and cyclo-static dataflow models to describe their data rates and static scheduling on FPGAs.

RIPL compares favourably compared to the Vivado HLS OpenCV library and C++ compiled with Vivado HLS. RIPL achieves between 54 and 191 frames per second (FPS) at 100MHz for four synthetic benchmarks, faster than HLS OpenCV in three cases. Two real world algorithms are implemented in RIPL, visual saliency and mean shift segmentation. For visual saliency algorithm, RIPL achieves 71 FPS compared to optimised C++ at 28 FPS. RIPL is also concise, being 5x shorter than C++ and 111x shorter than an equivalent direct dataflow implementation. For mean shift segmentation, RIPL achieves 7 FPS compared to optimised C++ on 64 CPU cores at 1.1, and RIPL is 10x shorter than the direct dataflow FPGA implementation.
Original languageEnglish
Article number7
JournalACM Transactions on Reconfigurable Technology and Systems
Issue number1
Publication statusPublished - 14 Mar 2018


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