Reconfigurable 2, 3 and 5-point DFT processing element for SDF FFT architecture using fast cyclic convolution algorithm

S. Bibin Sam Paul, A. X. Glittas, M. Sellathurai, G. Lakshminarayanan

Research output: Contribution to journalArticle

Abstract

In this Letter, a reconfigurable processing element (PE) for pipelined SDF FFT architecture is presented, which can be configured to compute 2, 3 and 5-point DFTs. Foremost, the proposed PE architecture for the 5-point DFT computation is designed by factorising the 5-point DFT computation operation into 2 × 2 cyclic convolution units and then the 2- and 3-point DFTs structures are mapped on to it using multiplexers. Thus, all three configurations are possible. In the case of prior 5-point PE designs, the PE can start its operation only after the arrival of all the five-input data, whereas the proposed PE completes a part of computation after the arrival of the first three inputs and reuse the same hardware to process the next two inputs. As a result, the proposed PE requires less hardware, at the same time, preserving the throughput of prior PE. The proposed PE required 25% less multiplier and one adder less compared to the Winograd algorithm based 5-input PE.

Original languageEnglish
Pages (from-to)592-594
Number of pages3
JournalElectronics Letters
Volume56
Issue number12
Early online date7 Apr 2020
DOIs
Publication statusPublished - 11 Jun 2020

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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