Real-Time Hardware Emulation for Spatial–Temporal Correlated Multiple Channels

  • Ling Yang
  • , Sheng Fang
  • , Yongfeng Zheng
  • , Yuetian Xie
  • , Yuan Ding
  • , Longjun Wang
  • , Boyu Hua
  • , Qiuming Zhu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

To reduce hardware consumption and improve the emulation accuracy of spatial-temporal correlated channel fading, this paper presents a novel emulation scheme based on the sum-of-cisoids (SOC) idea and develops a real-time hardware generation algorithm for complex harmonic frequencies(CHF). Specifically, this algorithm introduces random offsets to the parameters generated by the method of equal areas (MEA), ensuring the generation of multiple independent Gaussian random variables. Hardware measurement results demonstrate that the hardware resource consumption is lower than that of traditional methods. Furthermore, the spatial-temporal correlation of the generated channel fading closely matches the theoretical one, thereby validating the algorithm’s effectiveness.
Original languageEnglish
Title of host publication24th IEEE International Conference on Communication Technology (ICCT)
PublisherIEEE
Pages1441-1445
Number of pages5
ISBN (Electronic)9798350363760
DOIs
Publication statusPublished - 8 Apr 2025

Keywords

  • FPGA
  • channel fading emulation
  • spatial-temporal correlation
  • sum-of-cisoids (SOC)

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Computer Networks and Communications

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