Profile Guided Dataflow Transformation for FPGAs and CPUs

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6 Citations (Scopus)
50 Downloads (Pure)

Abstract

This paper proposes a new high-level approach for optimising field programmable gate array (FPGA) designs. FPGA designs are commonly implemented in low-level hardware description languages (HDLs), which lack the abstractions necessary for identifying opportunities for significant performance improvements. Using a computer vision case study, we show that modelling computation with dataflow abstractions enables substantial restructuring of FPGA designs before lowering to the HDL level, and also improve CPU performance. Using the CPU transformations, runtime is reduced by 43 %. Using the FPGA transformations, clock frequency is increased from 67MHz to 110MHz. Our results outperform commercial low-level HDL optimisations, showcasing dataflow program abstraction as an amenable computation model for highly effective FPGA optimisation.

Original languageEnglish
Pages (from-to)3-20
Number of pages18
JournalJournal of Signal Processing Systems
Volume87
Issue number1
Early online date2 Oct 2015
DOIs
Publication statusPublished - Apr 2017

Keywords

  • CPU
  • Dataflow
  • FPGA
  • Profiling
  • Transformations

ASJC Scopus subject areas

  • Control and Systems Engineering
  • Modelling and Simulation
  • Hardware and Architecture
  • Information Systems
  • Signal Processing
  • Theoretical Computer Science

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