Optimization of Correlation Coefficient Calculation for Channel Matrix Characterization on FPGA

Current and future wireless communication networks need to support the demand for an ever-increasing data rate. Modern wireless communication air-interfaces use various modulation schemes with embedded pilot signals that are used to probe the channel state information (CSI). Since frequency resources are increasingly scarce, it becomes favorable to reduce the bandwidth occupied by the resources allocated to the pilot signals without compromising the system performance. In a MIMO scenario, the knowledge of the correlation coefficients between receiving antennas can help to optimize the transmission reducing the need of additional transmitted data. In this paper, a novel hardware implementation for calculating the correlation coefficient between two unknown signals is presented. The proposed approach aims to maintain a low mean-square error (MSE) with the minimum number of samples. Additionally, hardware optimizations are applied to the design resulting in a valuable reduction of the required digital resources and latency. The measurements, based on Xilinx XC7Z020 FPGA SoC, are compared with the results in a simulation environment to demonstrate its efficacy in the supported 5G NR frequency ranges.