Abstract
This paper presents three optimal-complexity structures (I, II, III) for pipelined distributed arithmetic (DA) based least-mean-square (LMS) adaptive filter. The complexity of proposed structures is reduced by implementing offset-binary-coding (OBC) combinations of input samples on hardware. However, some non-OBC outputs are produced, and subsequently eliminated in the error computation during the initial clock cycles. For achieving more performance benefits, radix-4 OBC combinations of input samples are implemented with the proposed partial product generators. In addition, novel low-complexity implementations for the offset term, weight update block and shift-accumulate unit are also proposed. Analysis shows that byte-complexity of proposed structures vary linearly with the order of DA base unit, while their bit-complexity depends on the topology. All the structures show significant hardware savings, Structure-I has least critical-path and Structure-II, III offer superior convergence performance. Experimental results show that the Structure-I, II and III with 32 nd order filter provide savings 71.13%, 71.83% and 73.08% in area, 68.47%, 70.01% and 72.17% in power, 51.74%, 37.83% and 45.38% in area-per-throughput (APT), 47.33%, 33.72% and 43.19% in power-per-throughput (PPT), 55.11%, 59.66% and 64.20% in slice LUTs, 35.33%, 40.28% and 44.87% in flip-flops over the best existing scheme.
Original language | English |
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Pages (from-to) | 630-642 |
Number of pages | 13 |
Journal | IEEE Transactions on Circuits and Systems I: Regular Papers |
Volume | 66 |
Issue number | 2 |
DOIs | |
Publication status | Published - Feb 2019 |
Keywords
- Distributed arithmetic (DA)
- least mean square (LMS)
- look-up table (LUT)
- offset binary coding (OBC)
ASJC Scopus subject areas
- Electrical and Electronic Engineering