Optical clock distribution for a more efficient use of DRAMs

D. Litaize, M. P Y Desmulliez, J. H. Collet, P. Foulk

Research output: Contribution to journalArticlepeer-review

3 Citations (Scopus)


High-speed serial links offer the best usage of memory bus, given the still large access time of the memory. The reduction of the bus width in itself allows a cost-reduction of the backplane. An optical implementation that relies on the distribution of the clock to the processor and memory in order to control the phase of the signals is proposed.

Original languageEnglish
Pages (from-to)295-298
Number of pages4
JournalJournal of Optics A: Pure and Applied Optics
Issue number2
Publication statusPublished - Mar 1999


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