High-speed serial links offer the best usage of memory bus, given the still large access time of the memory. The reduction of the bus width in itself allows a cost-reduction of the backplane. An optical implementation that relies on the distribution of the clock to the processor and memory in order to control the phase of the signals is proposed.
|Number of pages||4|
|Journal||Journal of Optics A: Pure and Applied Optics|
|Publication status||Published - Mar 1999|