Optical clock distribution for a more efficient use of DRAMs

D. Litaize; M. P Y Desmulliez; J. H. Collet; P. Foulk

doi:10.1088/1464-4258/1/2/335

Optical clock distribution for a more efficient use of DRAMs

D. Litaize, M. P Y Desmulliez, J. H. Collet, P. Foulk

School of Engineering & Physical Sciences

Research output: Contribution to journal › Article › peer-review

3 Citations (Scopus)

Abstract

High-speed serial links offer the best usage of memory bus, given the still large access time of the memory. The reduction of the bus width in itself allows a cost-reduction of the backplane. An optical implementation that relies on the distribution of the clock to the processor and memory in order to control the phase of the signals is proposed.

Original language	English
Pages (from-to)	295-298
Number of pages	4
Journal	Journal of Optics A: Pure and Applied Optics
Volume	1
Issue number	2
DOIs	https://doi.org/10.1088/1464-4258/1/2/335
Publication status	Published - Mar 1999

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@article{30458e8dab824af682c250028a2f2d22,

title = "Optical clock distribution for a more efficient use of DRAMs",

abstract = "High-speed serial links offer the best usage of memory bus, given the still large access time of the memory. The reduction of the bus width in itself allows a cost-reduction of the backplane. An optical implementation that relies on the distribution of the clock to the processor and memory in order to control the phase of the signals is proposed.",

author = "D. Litaize and Desmulliez, {M. P Y} and Collet, {J. H.} and P. Foulk",

year = "1999",

month = mar,

doi = "10.1088/1464-4258/1/2/335",

language = "English",

volume = "1",

pages = "295--298",

journal = "Journal of Optics A: Pure and Applied Optics",

issn = "1741-3567",

publisher = "IOP Publishing ",

number = "2",

}

TY - JOUR

T1 - Optical clock distribution for a more efficient use of DRAMs

AU - Litaize, D.

AU - Desmulliez, M. P Y

AU - Collet, J. H.

AU - Foulk, P.

PY - 1999/3

Y1 - 1999/3

N2 - High-speed serial links offer the best usage of memory bus, given the still large access time of the memory. The reduction of the bus width in itself allows a cost-reduction of the backplane. An optical implementation that relies on the distribution of the clock to the processor and memory in order to control the phase of the signals is proposed.

AB - High-speed serial links offer the best usage of memory bus, given the still large access time of the memory. The reduction of the bus width in itself allows a cost-reduction of the backplane. An optical implementation that relies on the distribution of the clock to the processor and memory in order to control the phase of the signals is proposed.

UR - http://www.scopus.com/inward/record.url?scp=0033338732&partnerID=8YFLogxK

U2 - 10.1088/1464-4258/1/2/335

DO - 10.1088/1464-4258/1/2/335

M3 - Article

SN - 1741-3567

VL - 1

SP - 295

EP - 298

JO - Journal of Optics A: Pure and Applied Optics

JF - Journal of Optics A: Pure and Applied Optics

IS - 2

ER -

Optical clock distribution for a more efficient use of DRAMs

Abstract

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