On the impact of through-silicon-via-induced stress on 65-nm CMOS devices

Roshan Weerasekera; Hong Yu Li; Lim Wei Yi; Hu Sanming; Jinglin Shi; Je Minkyu; Keng Hwa Teo; Sanming Hu

doi:10.1109/LED.2012.2228158

On the impact of through-silicon-via-induced stress on 65-nm CMOS devices

Roshan Weerasekera^*
, Hong Yu Li
, Lim Wei Yi
, Hu Sanming
, Jinglin Shi
, Je Minkyu
, Keng Hwa Teo
, Sanming Hu

^*Corresponding author for this work

Research output: Contribution to journal › Article › peer-review

23 Citations (Scopus)

Abstract

Electrical evaluation of the impact of through-silicon via (TSV)-induced stress on 65-nm MOSFETs is presented in this letter. MOSFETs with varying widths and lengths were laid out at a minimum distance of 1.2 up to 16 μm from TSVs at different orientations. The TSV diameter, height, and dielectric barrier thickness are 8, 60, and 1 μm , respectively. Measured change of saturation current (I_on) of devices at the minimum distance is less than 4% for all the cases. The reliability of the devices was also investigated up to 1000 thermal cycles, between-55°C and 125°C. No significant change in MOSFET performance is observed in comparison with the measurements before thermal cycling.

Original language	English
Article number	6381443
Pages (from-to)	18-20
Number of pages	3
Journal	IEEE Electron Device Letters
Volume	34
Issue number	1
DOIs	https://doi.org/10.1109/LED.2012.2228158
Publication status	Published - 7 Jan 2013

Keywords

Keep-out zone (KOZ)
MOSFETs
three-dimensional integrated circuits (ICs)
through-silicon via (TSV)

ASJC Scopus subject areas

Electrical and Electronic Engineering
Electronic, Optical and Magnetic Materials

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10.1109/LED.2012.2228158

Cite this

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title = "On the impact of through-silicon-via-induced stress on 65-nm CMOS devices",

abstract = "Electrical evaluation of the impact of through-silicon via (TSV)-induced stress on 65-nm MOSFETs is presented in this letter. MOSFETs with varying widths and lengths were laid out at a minimum distance of 1.2 up to 16 μm from TSVs at different orientations. The TSV diameter, height, and dielectric barrier thickness are 8, 60, and 1 μm , respectively. Measured change of saturation current (Ion) of devices at the minimum distance is less than 4\% for all the cases. The reliability of the devices was also investigated up to 1000 thermal cycles, between-55°C and 125°C. No significant change in MOSFET performance is observed in comparison with the measurements before thermal cycling.",

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AU - Yi, Lim Wei

AU - Sanming, Hu

AU - Shi, Jinglin

AU - Minkyu, Je

AU - Teo, Keng Hwa

AU - Hu, Sanming

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AB - Electrical evaluation of the impact of through-silicon via (TSV)-induced stress on 65-nm MOSFETs is presented in this letter. MOSFETs with varying widths and lengths were laid out at a minimum distance of 1.2 up to 16 μm from TSVs at different orientations. The TSV diameter, height, and dielectric barrier thickness are 8, 60, and 1 μm , respectively. Measured change of saturation current (Ion) of devices at the minimum distance is less than 4% for all the cases. The reliability of the devices was also investigated up to 1000 thermal cycles, between-55°C and 125°C. No significant change in MOSFET performance is observed in comparison with the measurements before thermal cycling.

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On the impact of through-silicon-via-induced stress on 65-nm CMOS devices

Abstract

Keywords

ASJC Scopus subject areas

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