On the impact of through-silicon-via-induced stress on 65-nm CMOS devices

Roshan Weerasekera*, Hong Yu Li, Lim Wei Yi, Hu Sanming, Jinglin Shi, Je Minkyu, Keng Hwa Teo, Sanming Hu

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

23 Citations (Scopus)


Electrical evaluation of the impact of through-silicon via (TSV)-induced stress on 65-nm MOSFETs is presented in this letter. MOSFETs with varying widths and lengths were laid out at a minimum distance of 1.2 up to 16 μm from TSVs at different orientations. The TSV diameter, height, and dielectric barrier thickness are 8, 60, and 1 μm , respectively. Measured change of saturation current (Ion) of devices at the minimum distance is less than 4% for all the cases. The reliability of the devices was also investigated up to 1000 thermal cycles, between-55°C and 125°C. No significant change in MOSFET performance is observed in comparison with the measurements before thermal cycling.

Original languageEnglish
Article number6381443
Pages (from-to)18-20
Number of pages3
JournalIEEE Electron Device Letters
Issue number1
Publication statusPublished - 7 Jan 2013


  • Keep-out zone (KOZ)
  • three-dimensional integrated circuits (ICs)
  • through-silicon via (TSV)

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials


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