On the impact of through-silicon-via-induced stress on 65-nm CMOS devices

Roshan Weerasekera; Hong Yu Li; Lim Wei Yi; Hu Sanming; Jinglin Shi; Je Minkyu; Keng Hwa Teo; Sanming Hu

doi:10.1109/LED.2012.2228158

On the impact of through-silicon-via-induced stress on 65-nm CMOS devices

Roshan Weerasekera^*, Hong Yu Li, Lim Wei Yi, Hu Sanming, Jinglin Shi, Je Minkyu, Keng Hwa Teo, Sanming Hu

^*Corresponding author for this work

Research output: Contribution to journal › Article › peer-review

23 Citations (Scopus)

Abstract

Electrical evaluation of the impact of through-silicon via (TSV)-induced stress on 65-nm MOSFETs is presented in this letter. MOSFETs with varying widths and lengths were laid out at a minimum distance of 1.2 up to 16 μm from TSVs at different orientations. The TSV diameter, height, and dielectric barrier thickness are 8, 60, and 1 μm , respectively. Measured change of saturation current (I_on) of devices at the minimum distance is less than 4% for all the cases. The reliability of the devices was also investigated up to 1000 thermal cycles, between-55°C and 125°C. No significant change in MOSFET performance is observed in comparison with the measurements before thermal cycling.

Original language	English
Article number	6381443
Pages (from-to)	18-20
Number of pages	3
Journal	IEEE Electron Device Letters
Volume	34
Issue number	1
DOIs	https://doi.org/10.1109/LED.2012.2228158
Publication status	Published - 7 Jan 2013

Keywords

Keep-out zone (KOZ)
MOSFETs
three-dimensional integrated circuits (ICs)
through-silicon via (TSV)

ASJC Scopus subject areas

Electrical and Electronic Engineering
Electronic, Optical and Magnetic Materials

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Cite this

@article{0c817a343b854a119ee7afc320368609,

title = "On the impact of through-silicon-via-induced stress on 65-nm CMOS devices",

abstract = "Electrical evaluation of the impact of through-silicon via (TSV)-induced stress on 65-nm MOSFETs is presented in this letter. MOSFETs with varying widths and lengths were laid out at a minimum distance of 1.2 up to 16 μm from TSVs at different orientations. The TSV diameter, height, and dielectric barrier thickness are 8, 60, and 1 μm , respectively. Measured change of saturation current (Ion) of devices at the minimum distance is less than 4% for all the cases. The reliability of the devices was also investigated up to 1000 thermal cycles, between-55°C and 125°C. No significant change in MOSFET performance is observed in comparison with the measurements before thermal cycling.",

keywords = "Keep-out zone (KOZ), MOSFETs, three-dimensional integrated circuits (ICs), through-silicon via (TSV)",

author = "Roshan Weerasekera and Li, {Hong Yu} and Yi, {Lim Wei} and Hu Sanming and Jinglin Shi and Je Minkyu and Teo, {Keng Hwa} and Sanming Hu",

year = "2013",

month = jan,

day = "7",

doi = "10.1109/LED.2012.2228158",

language = "English",

volume = "34",

pages = "18--20",

journal = "IEEE Electron Device Letters",

issn = "0741-3106",

publisher = "IEEE",

number = "1",

}

TY - JOUR

T1 - On the impact of through-silicon-via-induced stress on 65-nm CMOS devices

AU - Weerasekera, Roshan

AU - Li, Hong Yu

AU - Yi, Lim Wei

AU - Sanming, Hu

AU - Shi, Jinglin

AU - Minkyu, Je

AU - Teo, Keng Hwa

AU - Hu, Sanming

PY - 2013/1/7

Y1 - 2013/1/7

N2 - Electrical evaluation of the impact of through-silicon via (TSV)-induced stress on 65-nm MOSFETs is presented in this letter. MOSFETs with varying widths and lengths were laid out at a minimum distance of 1.2 up to 16 μm from TSVs at different orientations. The TSV diameter, height, and dielectric barrier thickness are 8, 60, and 1 μm , respectively. Measured change of saturation current (Ion) of devices at the minimum distance is less than 4% for all the cases. The reliability of the devices was also investigated up to 1000 thermal cycles, between-55°C and 125°C. No significant change in MOSFET performance is observed in comparison with the measurements before thermal cycling.

AB - Electrical evaluation of the impact of through-silicon via (TSV)-induced stress on 65-nm MOSFETs is presented in this letter. MOSFETs with varying widths and lengths were laid out at a minimum distance of 1.2 up to 16 μm from TSVs at different orientations. The TSV diameter, height, and dielectric barrier thickness are 8, 60, and 1 μm , respectively. Measured change of saturation current (Ion) of devices at the minimum distance is less than 4% for all the cases. The reliability of the devices was also investigated up to 1000 thermal cycles, between-55°C and 125°C. No significant change in MOSFET performance is observed in comparison with the measurements before thermal cycling.

KW - Keep-out zone (KOZ)

KW - MOSFETs

KW - three-dimensional integrated circuits (ICs)

KW - through-silicon via (TSV)

UR - http://www.scopus.com/inward/record.url?scp=84871730318&partnerID=8YFLogxK

U2 - 10.1109/LED.2012.2228158

DO - 10.1109/LED.2012.2228158

M3 - Article

AN - SCOPUS:84871730318

SN - 0741-3106

VL - 34

SP - 18

EP - 20

JO - IEEE Electron Device Letters

JF - IEEE Electron Device Letters

IS - 1

M1 - 6381443

ER -

On the impact of through-silicon-via-induced stress on 65-nm CMOS devices

Abstract

Keywords

ASJC Scopus subject areas

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