Abstract
Reliability issues as a consequence of thermal/mechanical stresses created during packaging processes have been the main obstacle towards the realisation of high volume 3D Integrated Circuit (IC) integration technology for future microelectronics. However, there is no compelling laboratory-based metrology that can non-destructively measure or image stress/strain or warpage inside packaged chips, System-on-Chip (SoC) or System-in-Package (SiP), which is identified as a requirement by the International Technology Roadmap for Semiconductors (ITRS). In the work presented here, a triple-axis Jordan Valley Bede D1 X-ray diffractometer is used to develop a novel lab-based technique called X-ray diffraction 3-dimensional surface modelling (XRD/3DSM) for non-destructive analysis of manufacturing process-induced stress/warpage inside completely encapsulated packaged chips. The technique is demonstrated at room temperature and at elevated temperatures up to 115 degrees C by in situ XRD annealing experiments. The feasibility of this technique is confirmed through the characterisation of die stress inside encapsulated commercially available ultra-thin Quad Flat Non-lead (QFN) packages, as well as die stress in embedded QFN packages at various stages of the chip manufacturing process. (C) 2013 Elsevier B.V. All rights reserved.
| Original language | English |
|---|---|
| Pages (from-to) | 48-56 |
| Number of pages | 9 |
| Journal | Microelectronic Engineering |
| Volume | 117 |
| DOIs | |
| Publication status | Published - 1 Apr 2014 |
Keywords
- Non-destructive
- X-ray diffraction
- Stress
- Integrated circuit
- Embedded QFN package
- Warpage
- INTEGRATED-CIRCUITS
- STRESSES
Cite this
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Non-destructive laboratory-based X-ray diffraction mapping of warpage in Si die embedded in IC packages. / Wong, C. S.; Bennett, Nick S; Manessis, D.; Danilewsky, A.; McNally, P. J.
In: Microelectronic Engineering, Vol. 117, 01.04.2014, p. 48-56.Research output: Contribution to journal › Article
TY - JOUR
T1 - Non-destructive laboratory-based X-ray diffraction mapping of warpage in Si die embedded in IC packages
AU - Wong, C. S.
AU - Bennett, Nick S
AU - Manessis, D.
AU - Danilewsky, A.
AU - McNally, P. J.
PY - 2014/4/1
Y1 - 2014/4/1
N2 - Reliability issues as a consequence of thermal/mechanical stresses created during packaging processes have been the main obstacle towards the realisation of high volume 3D Integrated Circuit (IC) integration technology for future microelectronics. However, there is no compelling laboratory-based metrology that can non-destructively measure or image stress/strain or warpage inside packaged chips, System-on-Chip (SoC) or System-in-Package (SiP), which is identified as a requirement by the International Technology Roadmap for Semiconductors (ITRS). In the work presented here, a triple-axis Jordan Valley Bede D1 X-ray diffractometer is used to develop a novel lab-based technique called X-ray diffraction 3-dimensional surface modelling (XRD/3DSM) for non-destructive analysis of manufacturing process-induced stress/warpage inside completely encapsulated packaged chips. The technique is demonstrated at room temperature and at elevated temperatures up to 115 degrees C by in situ XRD annealing experiments. The feasibility of this technique is confirmed through the characterisation of die stress inside encapsulated commercially available ultra-thin Quad Flat Non-lead (QFN) packages, as well as die stress in embedded QFN packages at various stages of the chip manufacturing process. (C) 2013 Elsevier B.V. All rights reserved.
AB - Reliability issues as a consequence of thermal/mechanical stresses created during packaging processes have been the main obstacle towards the realisation of high volume 3D Integrated Circuit (IC) integration technology for future microelectronics. However, there is no compelling laboratory-based metrology that can non-destructively measure or image stress/strain or warpage inside packaged chips, System-on-Chip (SoC) or System-in-Package (SiP), which is identified as a requirement by the International Technology Roadmap for Semiconductors (ITRS). In the work presented here, a triple-axis Jordan Valley Bede D1 X-ray diffractometer is used to develop a novel lab-based technique called X-ray diffraction 3-dimensional surface modelling (XRD/3DSM) for non-destructive analysis of manufacturing process-induced stress/warpage inside completely encapsulated packaged chips. The technique is demonstrated at room temperature and at elevated temperatures up to 115 degrees C by in situ XRD annealing experiments. The feasibility of this technique is confirmed through the characterisation of die stress inside encapsulated commercially available ultra-thin Quad Flat Non-lead (QFN) packages, as well as die stress in embedded QFN packages at various stages of the chip manufacturing process. (C) 2013 Elsevier B.V. All rights reserved.
KW - Non-destructive
KW - X-ray diffraction
KW - Stress
KW - Integrated circuit
KW - Embedded QFN package
KW - Warpage
KW - INTEGRATED-CIRCUITS
KW - STRESSES
U2 - 10.1016/j.mee.2013.12.020
DO - 10.1016/j.mee.2013.12.020
M3 - Article
VL - 117
SP - 48
EP - 56
JO - Microelectronic Engineering
JF - Microelectronic Engineering
SN - 0167-9317
ER -