Modelling an optically interconnected FPGA for reconfigurable computing architectures

G. A. Russell; C. J. Moir; J. F. Snowdon

doi:10.1117/12.662718

Modelling an optically interconnected FPGA for reconfigurable computing architectures

G. A. Russell
, C. J. Moir
, J. F. Snowdon

School of Engineering & Physical Sciences

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

A series of electronic models, both analog and digital, have been developed to simulate the behaviour of a field programmable gate array chip with optoelectronics providing access to an optical interconnect fabric. The minimum latency of a 320Mbits^-1 system was found to be 158.5ns.

Original language	English
Title of host publication	Micro-Optics, VCSELs, and Photonic Interconnects II: Fabrication, Packaging, and Integration
Volume	6185
DOIs	https://doi.org/10.1117/12.662718
Publication status	Published - 2006
Event	Optical Sensing II - Strasbourg, France Duration: 3 Apr 2006 → 6 Apr 2006

Conference

Conference	Optical Sensing II
Country/Territory	France
City	Strasbourg
Period	3/04/06 → 6/04/06

Keywords

Field programmable gate arrays
Optically interconnected computing

Access to Document

10.1117/12.662718

Cite this

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title = "Modelling an optically interconnected FPGA for reconfigurable computing architectures",

abstract = "A series of electronic models, both analog and digital, have been developed to simulate the behaviour of a field programmable gate array chip with optoelectronics providing access to an optical interconnect fabric. The minimum latency of a 320Mbits-1 system was found to be 158.5ns.",

keywords = "Field programmable gate arrays, Optically interconnected computing",

author = "Russell, \{G. A.\} and Moir, \{C. J.\} and Snowdon, \{J. F.\}",

year = "2006",

doi = "10.1117/12.662718",

language = "English",

isbn = "0819462411",

volume = "6185",

booktitle = "Micro-Optics, VCSELs, and Photonic Interconnects II: Fabrication, Packaging, and Integration",

note = "Optical Sensing II ; Conference date: 03-04-2006 Through 06-04-2006",

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T1 - Modelling an optically interconnected FPGA for reconfigurable computing architectures

AU - Russell, G. A.

AU - Moir, C. J.

AU - Snowdon, J. F.

PY - 2006

Y1 - 2006

N2 - A series of electronic models, both analog and digital, have been developed to simulate the behaviour of a field programmable gate array chip with optoelectronics providing access to an optical interconnect fabric. The minimum latency of a 320Mbits-1 system was found to be 158.5ns.

AB - A series of electronic models, both analog and digital, have been developed to simulate the behaviour of a field programmable gate array chip with optoelectronics providing access to an optical interconnect fabric. The minimum latency of a 320Mbits-1 system was found to be 158.5ns.

KW - Field programmable gate arrays

KW - Optically interconnected computing

UR - https://www.scopus.com/pages/publications/33746681316

U2 - 10.1117/12.662718

DO - 10.1117/12.662718

M3 - Conference contribution

SN - 0819462411

SN - 9780819462411

VL - 6185

BT - Micro-Optics, VCSELs, and Photonic Interconnects II: Fabrication, Packaging, and Integration

T2 - Optical Sensing II

Y2 - 3 April 2006 through 6 April 2006

ER -

Modelling an optically interconnected FPGA for reconfigurable computing architectures

Abstract

Conference

Keywords

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