Abstract
A series of electronic models, both analog and digital, have been developed to simulate the behaviour of a field programmable gate array chip with optoelectronics providing access to an optical interconnect fabric. The minimum latency of a 320Mbits-1 system was found to be 158.5ns.
Original language | English |
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Title of host publication | Micro-Optics, VCSELs, and Photonic Interconnects II: Fabrication, Packaging, and Integration |
Volume | 6185 |
DOIs | |
Publication status | Published - 2006 |
Event | Optical Sensing II - Strasbourg, France Duration: 3 Apr 2006 → 6 Apr 2006 |
Conference
Conference | Optical Sensing II |
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Country/Territory | France |
City | Strasbourg |
Period | 3/04/06 → 6/04/06 |
Keywords
- Field programmable gate arrays
- Optically interconnected computing