Modelling an optically interconnected FPGA for reconfigurable computing architectures

G. A. Russell, C. J. Moir, J. F. Snowdon

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

A series of electronic models, both analog and digital, have been developed to simulate the behaviour of a field programmable gate array chip with optoelectronics providing access to an optical interconnect fabric. The minimum latency of a 320Mbits-1 system was found to be 158.5ns.

Original languageEnglish
Title of host publicationMicro-Optics, VCSELs, and Photonic Interconnects II: Fabrication, Packaging, and Integration
Volume6185
DOIs
Publication statusPublished - 2006
EventOptical Sensing II - Strasbourg, France
Duration: 3 Apr 20066 Apr 2006

Conference

ConferenceOptical Sensing II
CountryFrance
CityStrasbourg
Period3/04/066/04/06

Keywords

  • Field programmable gate arrays
  • Optically interconnected computing

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  • Cite this

    Russell, G. A., Moir, C. J., & Snowdon, J. F. (2006). Modelling an optically interconnected FPGA for reconfigurable computing architectures. In Micro-Optics, VCSELs, and Photonic Interconnects II: Fabrication, Packaging, and Integration (Vol. 6185) https://doi.org/10.1117/12.662718