Low quiescent current capacitorless small gain stages LDO with controlled pass transistors

Sadeque Reza Khan, Iram Nadeem

Research output: Contribution to journalArticlepeer-review

6 Citations (Scopus)


A low quiescent current 180-nm output-capacitorless low-dropout regulator with small-gain stages (SGSs) is presented in this paper. The proposed technique permits the regulator to distribute the load current into two power transistors depending on the demand of the load using a controller based on load variation criterion. SGSs are introduced to enhance loop gain without low-frequency poles. The proposed architecture does not require compensation capacitor. Thus, the active chip area is reduced to 73.59 µm × 36 µm. The measured results have shown that the fabricated circuit consumes a quiescent current of 1.8 µA at no load, regulating the output at 1 V with maximum output current of 50 mA from a voltage supply of 1.2 V. It achieves full range stability from 0 to 50 mA load current at a maximum 100 pF load capacitor.
Original languageEnglish
Pages (from-to)323–331
Number of pages9
JournalAnalog Integrated Circuits and Signal Processing
Issue number2
Publication statusPublished - Feb 2018


  • LDO regulator
  • Capacitorless
  • Quiescent current
  • Pass transistor
  • Small gain stage

ASJC Scopus subject areas

  • Electrical and Electronic Engineering


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