Low power and area efficient carry select adder

This paper presents a low power and area efficient Carry select adder (CSLA) motivated by generating half sum from half carry. Exploiting the incoming carry, a multiplexer selects the full sum as either half sum or its inversion for each bit. In order to obtain further reduction in gate count, for the generation of half sum, we have proposed an alternate logic which eliminates the use of EX-OR gate at each bit level. The proposed design shows 53.43% improvement in Area-Delay Product (ADP) and 46.04% in Power-Delay Product (PDP) compared to the common Boolean logic (CBL) based CSLA. As well, the ASIC synthesis results for the proposed architecture shows an average power reduction of 57.24% over conventional CSLA, 44.29% over BEC-CSLA, 19.25% over CBL-CSLA and 34.12% over SCG-CSLA for different bit-widths.