Low-complexity continuous-flow memory-based FFT architectures for real-valued signals

This paper presents two low-complexity continuous-flow memory-based fast Fourier transform (FFT) architectures (Type-I, II) for real-valued signals. Both the proposed designs employ split processing-elements (SPEs), however Type-I SPE processes four inputs while Type-II SPE processes two inputs in parallel. The SPE in Type-I design contains a half-complex multiplier and that of Type-II design contains a quarter-complex multiplier. Two new memory accessing schemes corresponding to each design is proposed. Analysis of computational complexities for both the architectures are carried out and compared with existing designs. It is found that Type-I architecture provides low-complexity in terms of registers and multiplexers while Type-II architecture provides low-complexity in terms of the multiplier. Application specific integrated circuit (ASIC) synthesis and field programmable gate array (FPGA) implementation results show that the proposed designs offer low-area, low-power and utilize less logic elements. For instance, 32-point Type-I real FFT offer requires 5.06% less area, 15.1% less power, 6.58% less sliced look-up table (SLUT) and 5.25% less FF while Type-II 47.76% less area, 43.64% power, 48.22% less SLUT and 43.48% less FF over the best existing scheme.