Developing a reconfigurable transceiver to support multiple protocols seamlessly and efficiently is an extremely tough task. Wireless standards such as wireless local area network (IEEE 802.11a/g) and WiMAX (IEEE 802.16e) incorporate block interleaving technique to overcome the occurrence of burst errors during transmission. Field Programmable Gate Array (FPGA) implementation of floor and modulus (MOD) functions to perform the two step permutation for attainingthe new index is quite complex. In this study, the authors propose a low complexity and area efficient reconfigurable architecture for multimode interleaver address generator to support multiple wireless standards. In addition, a novel MOD_row and MOD_column circuit are proposed to compute MOD function for row and column counter values, respectively. The proposed address generation circuitry supports BPSK, QPSK, 16-QAM and 64-QAM modulation schemes under all possible code rates. The reconfigurable address generator for various block size and modulationscheme are implemented on Xilinx Spartan XC3S400 FPGA and the functionalities are verified through simulation. The synthesis results of the proposed design shows a reduction of 60% in resource utilisation and an improvement of 46% in operating frequency over the existing approaches.
ASJC Scopus subject areas
- Hardware and Architecture
- Electrical and Electronic Engineering