Low-complex processing element architecture for successive cancellation decoder

Geethu Sathees Babu, Lakshmi Renuka Madala, Lakshminarayanan Gopalakrishnan, Mathini Sellathurai

Research output: Contribution to journalArticle

Abstract

A low-complexity design architecture for implementing the Successive Cancellation (SC) decoding algorithm for polar codes is presented. Hardware design of polar decoders is accomplished using SC decoding due to the reduced intricacy of the algorithm. Merged processing element (MPE) block is the primary area occupying factor of the SC decoder as it incorporates numerous sign and magnitude conversions. Two’s complement method is typically used in the MPE block of SC decoder. In this paper, a low-complex MPE architecture with minimal two’s complement conversion is proposed. A reformulation is also applied to the merged processing elements at the final stage of SC decoder to generate two output bits at a time. The proposed merged processing element thereby reduces the hardware complexity of the SC decoder and also reduces latency by an average of 64%. An SC decoder with code length 1024 and code rate 1/2 was designed and synthesized using 45-nm CMOS technology. The implementation results of the proposed decoder display significant improvement in the Technology Scaled Normalized Throughput (TSNT) value and an average 48% reduction in hardware complexity compared to the prevalent SC decoder architectures. Compared to the conventional SC decoder, the presented method displayed a 23% reduction in area.
Original languageEnglish
Pages (from-to)80-87
Number of pages8
JournalIntegration
Volume66
Early online date6 Feb 2019
DOIs
Publication statusPublished - May 2019

Keywords

  • ASIC
  • Polar codes
  • Processing element
  • Successive cancellation decoder

ASJC Scopus subject areas

  • Software
  • Hardware and Architecture
  • Electrical and Electronic Engineering

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