Joint undervolting and overclocking power scaling approximation on FPGAs

For applications in signal processing, Field Programmable Gate Arrays (FPGAs) are more flexible than Application Specific Integrated Circuits (ASICs), yet reconfigurable and still power and energy efficient to a degree. Undervolting and overclocking are approximate computing techniques that can further save power and energy, closing the efficiency gap by reducing the static/dynamic power and potentially speeding up the computation. However, these techniques may introduce bit level faults, which affect not only the computational correctness but also the security of the hardware. Understanding these fault behaviors provides necessary information for approximate implementation in low-power and secure design. In this work, we investigate joint undervolting and overclocking of AXI peripherals, specifically on-chip AXI memory access, using different commercial Xilinx Ultrascale+ heterogeneous MPSoCs with practical data movement between the ARM processor and the FPGA. Through experimental study we have observed fine-grained bit-flipping patterns when the voltage and clock are tuned beyond certain thresholds. By judging the probability of bit-flipping in terms of bit error rate, we propose a guideline for a balanced choice of voltage and frequency.