TY - JOUR
T1 - Improved convergent distributed arithmetic based low complexity pipelined least-meansquare filter
AU - Khan, Mohd Tasleem
AU - Shaik, Rafi Ahamed
AU - Matcha, Surya Prakash
N1 - Publisher Copyright:
© The Institution of Engineering and Technology 2018.
PY - 2018/5/15
Y1 - 2018/5/15
N2 - This study presents an improved convergent distributed arithmetic (DA)-based low complexity pipelined least-meansquare filter. The concept is based on a convex combination of two adaptive filters (ADFs) where the convergence performance of the combined filter is adjusted by the step-sizes of ADFs. The proposed technique replaced two ADF units by a single unit of the DA-based ADF. Further reduction in hardware complexity is achieved by sharing the filter partial products. Moreover, a bitlevel coefficient update unit is employed to minimise its hardware complexity. In addition, a novel low-cost strategy is presented to improve the convergence performance of the proposed filter by comparing the time-window corresponding to the maximum correlation of delayed error signals e(n - m) with a pre-defined window with n being time instant and m ∈ [1, 2]. Compared with the best existing scheme, the proposed design offers 46.42% fewer adders, 36.69% fewer registers and 18.75% fewer multiplexers for a 64th-order filter. Application specific integrated circuit synthesis results show that the proposed design occupies 37.10% less chip-area and consumes 24.79% less power. In addition, the proposed design provides 20.35% less area-delay-product and 4.76% less energy-per-sample for 64th order with the fourth-order base unit over the best existing scheme.
AB - This study presents an improved convergent distributed arithmetic (DA)-based low complexity pipelined least-meansquare filter. The concept is based on a convex combination of two adaptive filters (ADFs) where the convergence performance of the combined filter is adjusted by the step-sizes of ADFs. The proposed technique replaced two ADF units by a single unit of the DA-based ADF. Further reduction in hardware complexity is achieved by sharing the filter partial products. Moreover, a bitlevel coefficient update unit is employed to minimise its hardware complexity. In addition, a novel low-cost strategy is presented to improve the convergence performance of the proposed filter by comparing the time-window corresponding to the maximum correlation of delayed error signals e(n - m) with a pre-defined window with n being time instant and m ∈ [1, 2]. Compared with the best existing scheme, the proposed design offers 46.42% fewer adders, 36.69% fewer registers and 18.75% fewer multiplexers for a 64th-order filter. Application specific integrated circuit synthesis results show that the proposed design occupies 37.10% less chip-area and consumes 24.79% less power. In addition, the proposed design provides 20.35% less area-delay-product and 4.76% less energy-per-sample for 64th order with the fourth-order base unit over the best existing scheme.
UR - http://www.scopus.com/inward/record.url?scp=85057832489&partnerID=8YFLogxK
U2 - 10.1049/iet-cds.2018.0041
DO - 10.1049/iet-cds.2018.0041
M3 - Article
AN - SCOPUS:85057832489
SN - 1751-858X
VL - 12
SP - 792
EP - 801
JO - IET Circuits, Devices and Systems
JF - IET Circuits, Devices and Systems
IS - 6
ER -