Abstract
Sub-melt laser annealing is a promising technique to achieve the required sheet resistance and junction depth specifications for the 32 nm technology node and beyond. In order to obtain a production worthy process with minimal sheet resistance variation at a macroscopic and microscopic level, careful process optimization is required. While macroscopic variations can easily be addressed using the proper spatial power compensation it is more difficult to completely eliminate the micro scale non-uniformity which is intimately linked to the laser beam profile, the amount of overlaps and the scan pitch. In this work, we will present micro scale sheet resistance uniformity measurements for shallow 0.5 keV B junctions and zoom in on the underlying effect of multiple subsequent laser scans. A variety of characterization techniques are used to extract the relevant junction parameters and the role of different implantation and anneal parameters will be explored. It turns out that the observed sheet resistance decrease with increasing number of laser scans is caused on one hand by a temperature dependent increase of the activation level, and on the other hand, by a non-negligible temperature and concentration dependent diffusion component.
Original language | English |
---|---|
Title of host publication | 2008 16th IEEE International Conference on Advanced Thermal Processing of Semiconductors |
Pages | 135-140 |
Number of pages | 6 |
ISBN (Electronic) | 9781424419517 |
DOIs | |
Publication status | Published - 2008 |
Event | 16th IEEE International Conference on Advanced Thermal Processing of Semiconductors - Las Vegas, NV, United States Duration: 30 Sept 2008 → 3 Oct 2008 |
Conference
Conference | 16th IEEE International Conference on Advanced Thermal Processing of Semiconductors |
---|---|
Country/Territory | United States |
City | Las Vegas, NV |
Period | 30/09/08 → 3/10/08 |
ASJC Scopus subject areas
- Hardware and Architecture
- Electrical and Electronic Engineering