High-Performance VLSI Architecture of DLMS Adaptive Filter for Fast-Convergence and Low-MSE

Mohd. Tasleem Khan*, Rafi Ahamed Shaik

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

3 Citations (Scopus)

Abstract

This brief presents a high-performance VLSI architecture of delayed least mean square (DLMS) adaptive filter for fast-convergence and low-mean square error (MSE) using distributed arithmetic (DA). The proposed design estimates response against the adaptation delays using a parallel predictive adder tree followed by a shift accumulate (SA) unit. An efficient quantization scheme with two bits of scaled error signal is also suggested. Single SA unit for multiple DA bases is used to reduce the number of adders and registers. Simulation and synthesis results show that the proposed design for 32nd order provides 19.72% lesser area, 25.51% lesser power, lesser 28.89% MSE and 59.91% lesser MSE/area over the best existing design.

Original languageEnglish
Pages (from-to)2106-2110
Number of pages5
JournalIEEE Transactions on Circuits and Systems II: Express Briefs
Volume69
Issue number4
Early online date10 Jan 2022
DOIs
Publication statusPublished - Apr 2022

Keywords

  • adaptive filter (ADF)
  • Adder tree (AT)
  • least mean square (LMS)
  • mean square error (MSE)
  • pipelining

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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