High performance multiplierless serial pipelined VLSI architecture for real-valued FFT

This paper presents a high-performance multiplierless serial pipelined architecture for real-valued fast Fourier transform (FFT). A new data mapping scheme (DMS) is suggested for the proposed serial pipelined FFT architecture. The performance is enhanced by performing FFT computations in log- 2 N-1 stages followed by a select-store-feedback (SSF) stage, where N is the number of points in FFT. Further enhancement in performance is achieved by employing quarter-complex multiplierless unit made up of memory and combinational logic in every stage. The memory stores half number of partial products while the remaining partial products are taken care by external combinational logic. Compared with the best existing scheme, the proposed design reduces the computational workload on half-butterfly (H-BF) units by (2N-8). Application specific integrated circuit (ASIC) and field programmable gate array (FPGA) results show that the proposed design for 1024-point achieves 31.54% less area, 30.13% less power, 33.56% less area-delay product (ADP), 27.11% less sliced look-up tables (SLUTs) and 28.37% less flip-flops (FFs) as compared to the best existing scheme.