High-efficiency CMOS rectifier with minimized leakage and threshold cancellation features for low power bio-implants

Sadeque Reza Khan, GoangSeog Choi

Research output: Contribution to journalArticlepeer-review

20 Citations (Scopus)

Abstract

A high-efficiency architecture for full-wave CMOS rectifier is presented in this paper to solve the power supply issue of wirelessly-powered low-voltage biomedical implantable systems. It uses bootstrapped capacitors to reduce the effective threshold voltage and a CMOS inverter to minimize the reverse leakage. The designed architecture provides high Power Conversion Efficiency (PCE) at the cost of low dropout voltage. Therefore, this proposed architecture is a good candidate for low-voltage power supplies and large load current applications. The proposed rectifier is implemented in standard Samsung 0.18 µm CMOS technology in cadence environment. Simulation results demonstrate an improved voltage and power conversion efficiency with a small layout area compared with the best recently published results of CMOS rectifiers.
Original languageEnglish
Pages (from-to)67-75
Number of pages9
JournalMicroelectronics Journal
Volume66
DOIs
Publication statusPublished - Aug 2017

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Fingerprint

Dive into the research topics of 'High-efficiency CMOS rectifier with minimized leakage and threshold cancellation features for low power bio-implants'. Together they form a unique fingerprint.

Cite this