Heron: Modern Hardware Graph Reduction

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This paper presents Heron, an FPGA-based special purpose processor core for pure, non-strict functional languages. We co-design its language semantics and parametrised design, gaining a high reductions-per-cycle performance metric. The Heron core is energy efficient, performing up to six times as many reductions per cycle as GHC. Despite its infancy, a 193 MHz Heron core outperforms wall-clock time for a mid-range Intel i3 1.9 GHz mobile CPU for 5 of these benchmarks and is competitive with an Alder Lake Intel i7 CPU. Its performance-per-Watt shows that the Heron core is a compelling solution for embedded applications. The simplicity of Heron's design results in just 2% FPGA resource usage, paving the way for future single-chip parallelism, further improving absolute performance.
Original languageEnglish
Title of host publicationProceedings of IFL 2023
PublisherAssociation for Computing Machinery
Publication statusAccepted/In press - 6 Feb 2024
Event35th Symposium on Implementation and Application of Functional Languages 2023 - Braga, Portugal
Duration: 29 Aug 202331 Aug 2023


Conference35th Symposium on Implementation and Application of Functional Languages 2023
Abbreviated titleIFL 2023


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