Hardware implementation of CMAC and B-spline neural networks for embedded applications

Qiuye Zhao, Donald S. Reay

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Abstract

The cerebellar model articulation controller (CMAC) is particularly well suited to real-time embedded applications on account of its fast learning, local generalisation, and ease of either software or hardware implementation. Among its drawbacks are a large memory requirement and the inability to model function derivatives. These drawbacks are addressed by the B-spline neural network (BSNN) at the cost of greater computational complexity. This paper describes a simple modification to the CMAC network that yields characteristics equivalent to an order two BSNN, including function derivative modelling, for the same computational complexity as CMAC and is suitable for high speed hardware implementation in embedded applications. Two alternative approaches to its realisation, namely schematic entry and the Handel-C hardware programming language, using a field programmable gate array (FPGA) are described and compared. © 2005 IEEE.

Original languageEnglish
Title of host publicationProceedings of the International Joint Conference on Neural Networks, IJCNN 2005
Pages657-662
Number of pages6
Volume1
DOIs
Publication statusPublished - 2005
Event2005 International Joint Conference on Neural Networks - Montreal, QC, Canada
Duration: 31 Jul 20054 Aug 2005

Conference

Conference2005 International Joint Conference on Neural Networks
Abbreviated titleIJCNN 2005
CountryCanada
CityMontreal, QC
Period31/07/054/08/05

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