Abstract
The cerebellar model articulation controller (CMAC) is particularly well suited to real-time embedded applications on account of its fast learning, local generalisation, and ease of either software or hardware implementation. Among its drawbacks are a large memory requirement and the inability to model function derivatives. These drawbacks are addressed by the B-spline neural network (BSNN) at the cost of greater computational complexity. This paper describes a simple modification to the CMAC network that yields characteristics equivalent to an order two BSNN, including function derivative modelling, for the same computational complexity as CMAC and is suitable for high speed hardware implementation in embedded applications. Two alternative approaches to its realisation, namely schematic entry and the Handel-C hardware programming language, using a field programmable gate array (FPGA) are described and compared. © 2005 IEEE.
Original language | English |
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Title of host publication | Proceedings of the International Joint Conference on Neural Networks, IJCNN 2005 |
Pages | 657-662 |
Number of pages | 6 |
Volume | 1 |
DOIs | |
Publication status | Published - 2005 |
Event | 2005 IEEE International Joint Conference on Neural Networks - Montreal, Canada Duration: 31 Jul 2005 → 4 Aug 2005 |
Conference
Conference | 2005 IEEE International Joint Conference on Neural Networks |
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Abbreviated title | IJCNN 2005 |
Country/Territory | Canada |
City | Montreal |
Period | 31/07/05 → 4/08/05 |