Free-space digital optical processor based on InGaAs/CMOS hybrid optoelectronic chips

Andy C. Walker

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

An optoelectronic parallel data sorter was developed as a technology demonstrator as part of the Scottish Collaborative Initiative in Optoelectronic Sciences. The system is based on two arrays of smart pixels, produced by integration of InGaAs/GaAs multiple quantum well modulator/detectors with CMOS electronics connected by an optical system which implements a perfect shuffle of the 1,024 parallel data channels. The target clock frequency of 100 MHz gives a sorting capacity of up to 1024 16 bit words in less than 20 µs. This corresponds to an I/O data rate of 200 Gbit/s for each of the chips in the system.

Original languageEnglish
Title of host publicationProceedings of the 1997 Pacific Rim Conference on Lasers and Electro-Optics, CLEO/Pacific Rim
Pages275-276
Number of pages2
Publication statusPublished - 1997
Event1997 Pacific Rim Conference on Lasers and Electro-Optics, CLEO/Pacific Rim - Chiba, Japan
Duration: 14 Jul 199718 Jul 1997

Conference

Conference1997 Pacific Rim Conference on Lasers and Electro-Optics, CLEO/Pacific Rim
CountryJapan
CityChiba
Period14/07/9718/07/97

Fingerprint Dive into the research topics of 'Free-space digital optical processor based on InGaAs/CMOS hybrid optoelectronic chips'. Together they form a unique fingerprint.

Cite this