Field programmable gate array implementation of a neural network accelerator

D. S. Reay, T. C. Green, B. W. Williams

Research output: Contribution to journalArticle

Abstract

The use of a neural network to learn the nonlinear current profiles required to minimise torque ripple in a switched reluctance motor (SRM), at low to medium speeds, has been demonstrated using a digital signal processor (DSP). However, the DSP (Texas Instruments TMS320C25) implementation of a neural network in this application is a limiting factor on motor speed (if maximum current profile integrity is to be maintained). Fortunately, the neural network architecture used (cerebellar model articulation controller (CMAC)) is amenable to hardware implementation a point noted by Albus in one of his original papers and evidenced by at least one previous field programmable gate array (FPGA) implementation. Guided by the requirements of the switched reluctance motor application, a prototype accelerator based on a Xilinx XC4000 FPGA implementation of the neural network has been constructed that operates an order of magnitude faster than the DSP implementation.

Original languageEnglish
Pages (from-to)2/1-2/3
JournalIEE Colloquium (Digest)
Issue number61
Publication statusPublished - 9 Mar 1994
EventComputing and Control Division Colloquium on Hardware Implementation of Neural Networks and Fuzzy Logic - London, UK
Duration: 9 Mar 19949 Mar 1994

Fingerprint Dive into the research topics of 'Field programmable gate array implementation of a neural network accelerator'. Together they form a unique fingerprint.

  • Cite this