Effective operating system scheduling domain hierarchy for core-cache awareness

Jun Wei Lam, Ian Tan, Boon Leong Ong, Chang Kian Tan

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Citations (Scopus)


With the introduction of multi-core processors, a balance between access contention of the cache and availability of cached data for multiple cores has to be addressed. Processor manufacturers are finding this compromise through a combination of private and shared cache structures, where the last level cache (LLC) may not be shared across all processing cores. This poses an interesting opportunity for the operating system in ensuring minimum access time to the memory for optimal performance. Our proposed solution is to augment an existing scheduling domain hierarchy to be aware of the relationship between the processing cores and their respective LLCs in order to achieve improved performance. We focus on LLCs as the access time between local caches is minimal as compared to remote caches or main memory. In this paper, we show that there are marked improvements using a LU scientific benchmark and a chat-server application benchmark.

Original languageEnglish
Title of host publicationTENCON 2009 - 2009 IEEE Region 10 Conference
ISBN (Print)9781424445479
Publication statusPublished - 2009
Event2009 IEEE Region 10 Conference - Singapore, Singapore
Duration: 23 Nov 200926 Nov 2009


Conference2009 IEEE Region 10 Conference
Abbreviated titleTENCON 2009


  • Cache memories
  • Computer architecture
  • Operating systems kernel
  • Processor scheduling

ASJC Scopus subject areas

  • Computer Science Applications
  • Electrical and Electronic Engineering


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