Development of an efficient and flexible algorithm for implementing a digital household energy meter: an FPGA approach

This paper describes the development of an efficient algorithm that implements a flexible and affordable digital energy meter intended for home usage. As a first step, the algorithm is downloaded into an FPGA prototype board. The algorithm architecture comprises of four main modules: power, energy, billing and display. Two digitized inputs, which are assumed to come from single-phase voltage and single-phase current will be fed into the digital energy meter and the output is expected to be the energy consumed and the corresponding billing. The timing analysis has been performed on Aldec Active HDL, and ‘Synplify’has been used for circuit synthesis. Using digital synthetic test data it has been proven that the model has been tested successfully. This work forms the first phase of developing a commercial but affordable digital energy meter for home usage employing ASIC.