Design of a low drop-out voltage regulator using 0.13 µm cmos technology

Norhaida Binti Mustafa, Florence Choong*, Mamun Bin Ibne Reaz, Wan Irma Idayu Wan Mohd Nasir, Noorfazila Kamal, Abdul Mukit

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

1 Citation (Scopus)
242 Downloads (Pure)


In this paper, the design of a 4.5 V low drop out voltage regulator is proposed. Two-stage cascaded operational transconductance amplifier has been used as error amplifier. The two-stage amplifier is designed with body bias technique to reduce the drop out voltage of LDO regulator. In addition, PMOS is employed as a pass transistor yielding a more stable output voltage. The proposed regulator has a drop out voltage of 32.06 mV and power dissipation of 1.3593 mW. It is designed using a 0.13 µm standard CMOS process using Mentor Graphics software. The proposed design showed superiority over recent work yielding the lowest drop out voltage. The performance of the proposed design shows a promising opportunity to enhance chip level power management for SoC applications.

Original languageEnglish
Pages (from-to)1282-1298
Number of pages17
JournalJournal of Engineering Science and Technology
Issue number5
Publication statusPublished - May 2018


  • Body driven technique
  • Low drop out
  • Pass transistor
  • Transconductance amplifier
  • Voltage regulator

ASJC Scopus subject areas

  • General Engineering


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