Design of a low drop-out voltage regulator using 0.13 µm cmos technology

In this paper, the design of a 4.5 V low drop out voltage regulator is proposed. Two-stage cascaded operational transconductance amplifier has been used as error amplifier. The two-stage amplifier is designed with body bias technique to reduce the drop out voltage of LDO regulator. In addition, PMOS is employed as a pass transistor yielding a more stable output voltage. The proposed regulator has a drop out voltage of 32.06 mV and power dissipation of 1.3593 mW. It is designed using a 0.13 µm standard CMOS process using Mentor Graphics software. The proposed design showed superiority over recent work yielding the lowest drop out voltage. The performance of the proposed design shows a promising opportunity to enhance chip level power management for SoC applications.