The advances of chip scale packaging technologies have induced an increase of the density of solder joints in microelectronics products. Pitch sizes are consequently due to further decrease, leading to joint structures at sub 100µm dimensions. Stencil printing for wafer bumping with fine particle solder pastes is potentially a low-cost assembly solution for fine pitch solder joint interconnects. For ultra fine pitch applications stencil printing has been perceived to have reached its practical limits, in consequence a requirement to understand all the processes that impact on the performance of stencil printing at ultra fine pitch is needed. Paste roll, aperture filling & release, post print behaviour and paste open time need to be examined as experimental inputs, alongside the following parameters: fine particle Pb-free solder pastes and solder paste rheology, particle size distribution, metal content, flux type and stencil aperture attributes. The complexity in using stencil technology at such fine pitch geometries has indicated that the quality, consistency and yield are determined by a combination of variables that are involved in the stencil manufacture, paste formulation, and the print process performance of the paste from the stencil. With the WEEE and RoHS Directives being introduced to the electronics manufacturing industry we also have the change to Sn-Pb solders with Pb free alloys to consider. These changes in composition required for Pb free solder alloys and the behavioural changes caused by them during manufacturing processes mean that more process variables need to be understood. Along with the continual miniaturization in microelectronics, the number of variables and parameters that can be involved in stencil printing technology make tight process controls and consistent high yielding interconnects even more difficult to achieve. This paper will report on the advancements of stencil technology using novel micro-engineering techniques to achieve the quality required for printing at ultra fine pitches in terms of aperture tolerances, repeatability and side-wall smoothness. This study, coupled with the improvements in Pb free solder paste, shows that deposits can be produced at ultra fine pitch with types 6, 7 & 8 pastes. Tests also show that subtle differences in the performance of type-6 and type-7 and most recently type 8 mean that there should be careful selection of pastes made that are specific to application geometries. Investigations into the effects of different shaped aperture openings in the stencil also reveal that solder paste deposit volume can be controlled. Sufficient volumes of the fine particle solder paste are required during reflowing to obtain an adequate stand off between the flip chip device and substrate pad. Print consistency and uniformity of the bumps generated are also governed by the volume of solder paste for each deposit all of which will be shown to be more controllable with advanced electroformed stencils. © 2006 IEEE.
|Title of host publication||2006 Conference on High Density Microsystem Design and Packaging and Component Failure Analysis, HDP'06|
|Publication status||Published - 2006|
|Event||2006 Conference on High Density Microsystem Design and Packaging and Component Failure Analysis - Shanghai, China|
Duration: 27 Jun 2006 → 28 Jun 2006
|Conference||2006 Conference on High Density Microsystem Design and Packaging and Component Failure Analysis|
|Period||27/06/06 → 28/06/06|