A Dataflow IR for memory efficient RIPL compilation to FPGAs

Robert Stewart; Gregory John Michaelson; Deepayan Bhowmik; Paulo Garcia; Andy Wallace

doi:10.1007/978-3-319-49956-7_14

A Dataflow IR for memory efficient RIPL compilation to FPGAs

Robert Stewart^*, Gregory John Michaelson, Deepayan Bhowmik, Paulo Garcia, Andy Wallace

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

10 Citations (Scopus)

85 Downloads (Pure)

Abstract

Field programmable gate arrays (FPGAs) are fundamentally different to fixed processors architectures because their memory hierarchies can be tailored to the needs of an algorithm. FPGA compilers for high level languages are not hindered by fixed memory hierarchies. The constraint when compiling to FPGAs is the availability of resources. In this paper we describe how the dataflow intermediary of our declarative FPGA image processing DSL called RIPL (Rathlin Image Processing Language) enables us to constrain memory. We use five benchmarks to demonstrate that memory use with RIPL is comparable to the Vivado HLS OpenCV library without the need for language pragmas to guide hardware synthesis. The benchmarks also show that RIPL is more expressive than the Darkroom FPGA image processing language.

Original language	English
Title of host publication	Algorithms and Architectures for Parallel Processing
Subtitle of host publication	ICA3PP 2016 Collocated Workshops: SCDT, TAPEMS, BigTrust, UCER, DLMCS, Granada, Spain, December 14-16, 2016, Proceedings
Publisher	Springer
Pages	174-188
Number of pages	15
ISBN (Electronic)	9783319499567
ISBN (Print)	9783319499550
DOIs	https://doi.org/10.1007/978-3-319-49956-7_14
Publication status	Published - 2016
Event	16th International Conference on Algorithms and Architectures for Parallel Processing - ICA3PP 2016: 1st International Workshop on Data Locality in Modern Computing Systems, DLMCS 2016 - Granada, Spain Duration: 14 Dec 2016 → 16 Dec 2016

Publication series

Name	Lecture Notes in Computer Science
Publisher	Springer
Volume	10049
ISSN (Print)	0302-9743
ISSN (Electronic)	1611-3349

Conference

Conference	16th International Conference on Algorithms and Architectures for Parallel Processing - ICA3PP 2016
Country/Territory	Spain
City	Granada
Period	14/12/16 → 16/12/16

Keywords

Data locality
Domain specific languages
FPGAs

ASJC Scopus subject areas

Theoretical Computer Science
General Computer Science

Access to Document

10.1007/978-3-319-49956-7_14

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Cite this

Stewart, R., Michaelson, G. J., Bhowmik, D., Garcia, P., & Wallace, A. (2016). A Dataflow IR for memory efficient RIPL compilation to FPGAs. In Algorithms and Architectures for Parallel Processing: ICA3PP 2016 Collocated Workshops: SCDT, TAPEMS, BigTrust, UCER, DLMCS, Granada, Spain, December 14-16, 2016, Proceedings (pp. 174-188). (Lecture Notes in Computer Science; Vol. 10049). Springer. https://doi.org/10.1007/978-3-319-49956-7_14

Stewart, Robert ; Michaelson, Gregory John ; Bhowmik, Deepayan et al. / A Dataflow IR for memory efficient RIPL compilation to FPGAs. Algorithms and Architectures for Parallel Processing: ICA3PP 2016 Collocated Workshops: SCDT, TAPEMS, BigTrust, UCER, DLMCS, Granada, Spain, December 14-16, 2016, Proceedings. Springer, 2016. pp. 174-188 (Lecture Notes in Computer Science).

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abstract = "Field programmable gate arrays (FPGAs) are fundamentally different to fixed processors architectures because their memory hierarchies can be tailored to the needs of an algorithm. FPGA compilers for high level languages are not hindered by fixed memory hierarchies. The constraint when compiling to FPGAs is the availability of resources. In this paper we describe how the dataflow intermediary of our declarative FPGA image processing DSL called RIPL (Rathlin Image Processing Language) enables us to constrain memory. We use five benchmarks to demonstrate that memory use with RIPL is comparable to the Vivado HLS OpenCV library without the need for language pragmas to guide hardware synthesis. The benchmarks also show that RIPL is more expressive than the Darkroom FPGA image processing language.",

keywords = "Data locality, Domain specific languages, FPGAs",

author = "Robert Stewart and Michaelson, {Gregory John} and Deepayan Bhowmik and Paulo Garcia and Andy Wallace",

year = "2016",

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booktitle = "Algorithms and Architectures for Parallel Processing",

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Stewart, R , Michaelson, GJ, Bhowmik, D, Garcia, P & Wallace, A 2016, A Dataflow IR for memory efficient RIPL compilation to FPGAs. in Algorithms and Architectures for Parallel Processing: ICA3PP 2016 Collocated Workshops: SCDT, TAPEMS, BigTrust, UCER, DLMCS, Granada, Spain, December 14-16, 2016, Proceedings. Lecture Notes in Computer Science, vol. 10049, Springer, pp. 174-188, 16th International Conference on Algorithms and Architectures for Parallel Processing - ICA3PP 2016, Granada, Spain, 14/12/16. https://doi.org/10.1007/978-3-319-49956-7_14

A Dataflow IR for memory efficient RIPL compilation to FPGAs. / Stewart, Robert ; Michaelson, Gregory John; Bhowmik, Deepayan et al.
Algorithms and Architectures for Parallel Processing: ICA3PP 2016 Collocated Workshops: SCDT, TAPEMS, BigTrust, UCER, DLMCS, Granada, Spain, December 14-16, 2016, Proceedings. Springer, 2016. p. 174-188 (Lecture Notes in Computer Science; Vol. 10049).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

TY - GEN

T1 - A Dataflow IR for memory efficient RIPL compilation to FPGAs

AU - Stewart, Robert

AU - Michaelson, Gregory John

AU - Bhowmik, Deepayan

AU - Garcia, Paulo

AU - Wallace, Andy

PY - 2016

Y1 - 2016

N2 - Field programmable gate arrays (FPGAs) are fundamentally different to fixed processors architectures because their memory hierarchies can be tailored to the needs of an algorithm. FPGA compilers for high level languages are not hindered by fixed memory hierarchies. The constraint when compiling to FPGAs is the availability of resources. In this paper we describe how the dataflow intermediary of our declarative FPGA image processing DSL called RIPL (Rathlin Image Processing Language) enables us to constrain memory. We use five benchmarks to demonstrate that memory use with RIPL is comparable to the Vivado HLS OpenCV library without the need for language pragmas to guide hardware synthesis. The benchmarks also show that RIPL is more expressive than the Darkroom FPGA image processing language.

AB - Field programmable gate arrays (FPGAs) are fundamentally different to fixed processors architectures because their memory hierarchies can be tailored to the needs of an algorithm. FPGA compilers for high level languages are not hindered by fixed memory hierarchies. The constraint when compiling to FPGAs is the availability of resources. In this paper we describe how the dataflow intermediary of our declarative FPGA image processing DSL called RIPL (Rathlin Image Processing Language) enables us to constrain memory. We use five benchmarks to demonstrate that memory use with RIPL is comparable to the Vivado HLS OpenCV library without the need for language pragmas to guide hardware synthesis. The benchmarks also show that RIPL is more expressive than the Darkroom FPGA image processing language.

KW - Data locality

KW - Domain specific languages

KW - FPGAs

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AN - SCOPUS:85007338171

SN - 9783319499550

T3 - Lecture Notes in Computer Science

SP - 174

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Stewart R , Michaelson GJ, Bhowmik D, Garcia P, Wallace A. A Dataflow IR for memory efficient RIPL compilation to FPGAs. In Algorithms and Architectures for Parallel Processing: ICA3PP 2016 Collocated Workshops: SCDT, TAPEMS, BigTrust, UCER, DLMCS, Granada, Spain, December 14-16, 2016, Proceedings. Springer. 2016. p. 174-188. (Lecture Notes in Computer Science). Epub 2016 Nov 19. doi: 10.1007/978-3-319-49956-7_14

A Dataflow IR for memory efficient RIPL compilation to FPGAs

Abstract

Publication series

Conference

Keywords

ASJC Scopus subject areas

Access to Document

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Open dataset for "A Dataflow IR for Memory Efficient RIPL Compilation to FPGAs" in DLMCS 2016

Cite this

A Dataflow IR for memory efficient RIPL compilation to FPGAs

Abstract

Publication series

Conference

Keywords

ASJC Scopus subject areas

Access to Document

Other files and links

Fingerprint

Datasets

Open dataset for "A Dataflow IR for Memory Efficient RIPL Compilation to FPGAs" in DLMCS 2016

Cite this