A Dataflow IR for memory efficient RIPL compilation to FPGAs

Robert Stewart, Gregory John Michaelson, Deepayan Bhowmik, Paulo Garcia, Andy Wallace

Research output: Chapter in Book/Report/Conference proceedingConference contribution

6 Citations (Scopus)
29 Downloads (Pure)

Abstract

Field programmable gate arrays (FPGAs) are fundamentally different to fixed processors architectures because their memory hierarchies can be tailored to the needs of an algorithm. FPGA compilers for high level languages are not hindered by fixed memory hierarchies. The constraint when compiling to FPGAs is the availability of resources. In this paper we describe how the dataflow intermediary of our declarative FPGA image processing DSL called RIPL (Rathlin Image Processing Language) enables us to constrain memory. We use five benchmarks to demonstrate that memory use with RIPL is comparable to the Vivado HLS OpenCV library without the need for language pragmas to guide hardware synthesis. The benchmarks also show that RIPL is more expressive than the Darkroom FPGA image processing language.

Original languageEnglish
Title of host publicationAlgorithms and Architectures for Parallel Processing
Subtitle of host publicationICA3PP 2016 Collocated Workshops: SCDT, TAPEMS, BigTrust, UCER, DLMCS, Granada, Spain, December 14-16, 2016, Proceedings
PublisherSpringer International Publishing
Pages174-188
Number of pages15
ISBN (Electronic)9783319499567
ISBN (Print)9783319499550
DOIs
Publication statusPublished - 2016
Event16th International Conference on Algorithms and Architectures for Parallel Processing - ICA3PP 2016: 1st International Workshop on Data Locality in Modern Computing Systems, DLMCS 2016 - Granada, Spain
Duration: 14 Dec 201616 Dec 2016

Publication series

NameLecture Notes in Computer Science
PublisherSpringer
Volume10049
ISSN (Print)0302-9743
ISSN (Electronic)1611-3349

Conference

Conference16th International Conference on Algorithms and Architectures for Parallel Processing - ICA3PP 2016
CountrySpain
CityGranada
Period14/12/1616/12/16

Keywords

  • Data locality
  • Domain specific languages
  • FPGAs

ASJC Scopus subject areas

  • Theoretical Computer Science
  • Computer Science(all)

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    Stewart, R., Michaelson, G. J., Bhowmik, D., Garcia, P., & Wallace, A. (2016). A Dataflow IR for memory efficient RIPL compilation to FPGAs. In Algorithms and Architectures for Parallel Processing: ICA3PP 2016 Collocated Workshops: SCDT, TAPEMS, BigTrust, UCER, DLMCS, Granada, Spain, December 14-16, 2016, Proceedings (pp. 174-188). (Lecture Notes in Computer Science; Vol. 10049). Springer International Publishing. https://doi.org/10.1007/978-3-319-49956-7_14