Construction of an optoelectronic bitonic sorter based on CMOS/InGaAs smart pixel technology

A. C. Walker; M. P Y Desmulliez; F. A P Tooley; D. T. Neilson; J. A B Dines; D. A. Baillie; S. M. Prince; L. C. Wilkinson; M. R. Taghizadeh; P. Blair; J. F. Snowdon; B. S. Wherrett; C. Stanley; F. Pottier; I. Underwood

Construction of an optoelectronic bitonic sorter based on CMOS/InGaAs smart pixel technology

A. C. Walker, M. P Y Desmulliez, F. A P Tooley, D. T. Neilson, J. A B Dines, D. A. Baillie, S. M. Prince, L. C. Wilkinson, M. R. Taghizadeh, P. Blair, J. F. Snowdon, B. S. Wherrett, C. Stanley, F. Pottier, I. Underwood

School of Engineering & Physical Sciences

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

7 Citations (Scopus)

Abstract

The Scottish Collaborative Initiative in Optoelectronic Sciences (SCIOS) is developing an optoelectronic parallel sorter using CMOS/InGaAs hybrid technology. We describe the design of a system with the potential of sorting 1024 8-bit words in 10 µs. The system is based on 32-by-32 arrays of smart pixels produced by solder-assembly of strained InGaAs/GaAs MQW modulator/detectors with CMOS electronics. These devices are linked by an optical perfect shuffle interconnect. The functionality of each processing node, as required by the algorithm, is selected by optical control signals which are circulated along with the optical data. Various physical constraints, including optics limitations, laser power requirements and heat dissipation, have been investigated.

Original language	English
Title of host publication	Proceedings of the 2nd International Conference on Massively Parallel Processing Using Optical Interconnections (MPPOI'95)
Pages	180-187
Number of pages	8
Publication status	Published - 1995
Event	2nd International Conference on Massively Parallel Processing Using Optical Interconnections - San Antonio, TX, United States Duration: 23 Oct 1995 → 24 Oct 1995

Conference

Conference	2nd International Conference on Massively Parallel Processing Using Optical Interconnections
Abbreviated title	MPPOI'95
Country/Territory	United States
City	San Antonio, TX
Period	23/10/95 → 24/10/95

Cite this

Walker, A. C., Desmulliez, M. P. Y., Tooley, F. A. P., Neilson, D. T., Dines, J. A. B., Baillie, D. A., Prince, S. M., Wilkinson, L. C., Taghizadeh, M. R., Blair, P., Snowdon, J. F., Wherrett, B. S., Stanley, C., Pottier, F., & Underwood, I. (1995). Construction of an optoelectronic bitonic sorter based on CMOS/InGaAs smart pixel technology. In Proceedings of the 2nd International Conference on Massively Parallel Processing Using Optical Interconnections (MPPOI'95) (pp. 180-187)

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title = "Construction of an optoelectronic bitonic sorter based on CMOS/InGaAs smart pixel technology",

abstract = "The Scottish Collaborative Initiative in Optoelectronic Sciences (SCIOS) is developing an optoelectronic parallel sorter using CMOS/InGaAs hybrid technology. We describe the design of a system with the potential of sorting 1024 8-bit words in 10 µs. The system is based on 32-by-32 arrays of smart pixels produced by solder-assembly of strained InGaAs/GaAs MQW modulator/detectors with CMOS electronics. These devices are linked by an optical perfect shuffle interconnect. The functionality of each processing node, as required by the algorithm, is selected by optical control signals which are circulated along with the optical data. Various physical constraints, including optics limitations, laser power requirements and heat dissipation, have been investigated.",

author = "Walker, {A. C.} and Desmulliez, {M. P Y} and Tooley, {F. A P} and Neilson, {D. T.} and Dines, {J. A B} and Baillie, {D. A.} and Prince, {S. M.} and Wilkinson, {L. C.} and Taghizadeh, {M. R.} and P. Blair and Snowdon, {J. F.} and Wherrett, {B. S.} and C. Stanley and F. Pottier and I. Underwood",

year = "1995",

language = "English",

pages = "180--187",

booktitle = "Proceedings of the 2nd International Conference on Massively Parallel Processing Using Optical Interconnections (MPPOI'95)",

note = "2nd International Conference on Massively Parallel Processing Using Optical Interconnections, MPPOI'95 ; Conference date: 23-10-1995 Through 24-10-1995",

}

Walker, AC, Desmulliez, MPY, Tooley, FAP, Neilson, DT, Dines, JAB, Baillie, DA, Prince, SM, Wilkinson, LC, Taghizadeh, MR, Blair, P, Snowdon, JF, Wherrett, BS, Stanley, C, Pottier, F & Underwood, I 1995, Construction of an optoelectronic bitonic sorter based on CMOS/InGaAs smart pixel technology. in Proceedings of the 2nd International Conference on Massively Parallel Processing Using Optical Interconnections (MPPOI'95). pp. 180-187, 2nd International Conference on Massively Parallel Processing Using Optical Interconnections, San Antonio, TX, United States, 23/10/95.

Construction of an optoelectronic bitonic sorter based on CMOS/InGaAs smart pixel technology. / Walker, A. C.; Desmulliez, M. P Y; Tooley, F. A P et al.
Proceedings of the 2nd International Conference on Massively Parallel Processing Using Optical Interconnections (MPPOI'95). 1995. p. 180-187.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

TY - GEN

T1 - Construction of an optoelectronic bitonic sorter based on CMOS/InGaAs smart pixel technology

AU - Walker, A. C.

AU - Desmulliez, M. P Y

AU - Tooley, F. A P

AU - Neilson, D. T.

AU - Dines, J. A B

AU - Baillie, D. A.

AU - Prince, S. M.

AU - Wilkinson, L. C.

AU - Taghizadeh, M. R.

AU - Blair, P.

AU - Snowdon, J. F.

AU - Wherrett, B. S.

AU - Stanley, C.

AU - Pottier, F.

AU - Underwood, I.

PY - 1995

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N2 - The Scottish Collaborative Initiative in Optoelectronic Sciences (SCIOS) is developing an optoelectronic parallel sorter using CMOS/InGaAs hybrid technology. We describe the design of a system with the potential of sorting 1024 8-bit words in 10 µs. The system is based on 32-by-32 arrays of smart pixels produced by solder-assembly of strained InGaAs/GaAs MQW modulator/detectors with CMOS electronics. These devices are linked by an optical perfect shuffle interconnect. The functionality of each processing node, as required by the algorithm, is selected by optical control signals which are circulated along with the optical data. Various physical constraints, including optics limitations, laser power requirements and heat dissipation, have been investigated.

AB - The Scottish Collaborative Initiative in Optoelectronic Sciences (SCIOS) is developing an optoelectronic parallel sorter using CMOS/InGaAs hybrid technology. We describe the design of a system with the potential of sorting 1024 8-bit words in 10 µs. The system is based on 32-by-32 arrays of smart pixels produced by solder-assembly of strained InGaAs/GaAs MQW modulator/detectors with CMOS electronics. These devices are linked by an optical perfect shuffle interconnect. The functionality of each processing node, as required by the algorithm, is selected by optical control signals which are circulated along with the optical data. Various physical constraints, including optics limitations, laser power requirements and heat dissipation, have been investigated.

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M3 - Conference contribution

SP - 180

EP - 187

BT - Proceedings of the 2nd International Conference on Massively Parallel Processing Using Optical Interconnections (MPPOI'95)

T2 - 2nd International Conference on Massively Parallel Processing Using Optical Interconnections

Y2 - 23 October 1995 through 24 October 1995

ER -

Construction of an optoelectronic bitonic sorter based on CMOS/InGaAs smart pixel technology

Abstract

Conference

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