Construction of a Low Multiplicative Complexity GF (24) Inversion Circuit for Compact AES S-Box

Jia Jun Tay, M. L. Dennis Wong, Ming Ming Wong, Cishen Zhang, Ismat Hijazin

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)
79 Downloads (Pure)


In this work, we construct a compact composite AES S-Box by deriving a new low multiplicative complexity GF (2 4 ) inversion circuit. A deterministic tree search algorithm is applied to search for constructions that are optimum in terms of multiplicative complexity. From the results, the circuit with the smallest gate count is selected for GF (2 ) inversion. To the best of our knowledge, the proposed AES S-Box requires the smallest gate count to date with the size of 112 gates and depth of 25 gates.
Original languageEnglish
Title of host publicationTENCON 2018 - 2018 IEEE Region 10 Conference
Number of pages5
ISBN (Electronic)9781538654576
Publication statusPublished - 25 Feb 2019
EventIEEE TENCON 2018 - Jeju, Korea, Democratic People's Republic of
Duration: 28 Oct 201831 Oct 2018


ConferenceIEEE TENCON 2018
Country/TerritoryKorea, Democratic People's Republic of
Internet address


  • Advanced Encryption Standard (AES)
  • S-Box
  • composite field arithmetic (CFA)
  • low multiplicative complexity

ASJC Scopus subject areas

  • Computer Science Applications
  • Electrical and Electronic Engineering


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