Abstract
In this study, the authors categorise all of the feasible constructions for the composite Galois field GF(((22)2)2) Advanced Encryption Standard (AES) S-box into four main architectures by their field representations and their algebraic properties. For each of the categories, a new optimisation scheme which exploits algebraic normal form representation followed by a sub-structure sharing optimisation is presented. This is performed by converting the subfield GF((22) inversion into several logical expressions, which will be in turn reduced using a common sub-expression elimination algorithm. The authors show that this technique can effectively reduce the total area gate count as well as the critical path gate count in composite field AES S-boxes. The resulting architecture that achieves maximum reduction in both total area coverage and critical path gate count is found and reported. The hardware implementations of the authors proposed AES S-boxes, along with their performance and cost are presented and discussed.
Original language | English |
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Pages (from-to) | 471-476 |
Number of pages | 6 |
Journal | IET Circuits, Devices and Systems |
Volume | 5 |
Issue number | 6 |
DOIs | |
Publication status | Published - Nov 2011 |
ASJC Scopus subject areas
- Control and Systems Engineering
- Electrical and Electronic Engineering