Compact FPGA implementation of PRESENT with Boolean S-Box

J. J. Tay, M. L. Dennis Wong, M. M. Wong, C. Zhang, I. Hijazin

Research output: Chapter in Book/Report/Conference proceedingConference contribution

44 Citations (Scopus)


Ever since the conception of the ideology known as the Internet of Things (IoT), our world is slowly approaching the brink of mankind's next technological revolution. The realization of IoT requires an enormous amount of sensor nodes to acquire inputs from the connected objects. Due to the lightweight nature of these sensors, constraints emerge in the form of limited power supply and area for the implementation of information security mechanism. To ensure security in the data transmitted by these sensors, lightweight cryptographic solutions are required. In this work, our goal is to implement a compact PRESENT cipher onto a Field Programmable Gate Array (FPGA) platform. Our proposed design uses an 8-bit datapath to reduce hardware size. Instead of a traditional look-up table (LUT) based S-Box, we have implemented a Boolean S-Box through Karnaugh mapping. Further factorization is also done to reduce the size of the Boolean S-Box. As a result, we have achieved the smallest FPGA implementation of the PRESENT cipher to date, requiring only 62 slices on the Virtex-5 XC5VLX50 platform. Our design also features a respectable throughput of 51.32 Mbps at the maximum frequency of 236.574 MHz.

Original languageEnglish
Title of host publicationProceedings of the 6th Asia Symposium on Quality Electronic Design, ASQED 2015
Number of pages5
ISBN (Electronic)9781467374958
Publication statusPublished - Sept 2015
Event6th Asia Symposium on Quality Electronic Design 2015 - Kuala Lumpur, Malaysia
Duration: 4 Aug 20155 Aug 2015


Conference6th Asia Symposium on Quality Electronic Design 2015
Abbreviated titleASQED 2015
CityKuala Lumpur


  • block cipher
  • Boolean
  • FPGA
  • lightweight

ASJC Scopus subject areas

  • Electrical and Electronic Engineering


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