Abstract
Modern computing paradigm such as the Internet of Things demands edge devices with limited resources to be capable of complex computing functions. In this work, we discuss a relatively new approach to combinational circuit optimization based on a low multiplicative complexity heuristic. The purpose of the optimization heuristic is to produce low gate count circuit to enable complex transformation to fit in devices that operate in ultra-constrained environments. We explain the concepts behind the heuristic and review the original optimization algorithm based on the heuristic. A new approach is then proposed to eliminate reliance on randomness in the original algorithm to improve computational time and quality of results.
| Original language | English |
|---|---|
| Title of host publication | 2018 6th Edition of International Conference on Wireless Networks and Embedded Systems (WECON) |
| Publisher | IEEE |
| Pages | 27-30 |
| Number of pages | 4 |
| ISBN (Electronic) | 9781538670507 |
| DOIs | |
| Publication status | Published - 1 Aug 2019 |
| Event | 6th International Conference on Wireless Networks and Embedded Systems 2018 - Rajpura, Punjab, India Duration: 16 Nov 2018 → 17 Nov 2018 |
Conference
| Conference | 6th International Conference on Wireless Networks and Embedded Systems 2018 |
|---|---|
| Abbreviated title | WECON 2018 |
| Country/Territory | India |
| City | Rajpura, Punjab |
| Period | 16/11/18 → 17/11/18 |
Keywords
- Combinational logic
- low gate count
- multiplicative complexity
ASJC Scopus subject areas
- Instrumentation
- Computer Networks and Communications
- Signal Processing
- Electrical and Electronic Engineering