Circuit and system design for optimal lightweight AES encryption on FPGA

The substitution box (or commonly termed as S-Box) is a non-linear transformation, and known as the bottleneck of the overall operation in AES cipher. Due to recent emergence of high performance and lightweight applications, the required optimum AES cipher has to be both hardware cost effective and computationally efficient. In this study, we implemented various S-box architectures in AES encryption in order to perform an in-depth hardware analysis on FPGA platform. These architectures are the hard-coded LUT S-box, the pure combinatorial S-box using composite field arithmetic (CFA), the pipelined version of CFA S-Box, the CFA AES S-box using direct computation and Linear Feedback Shift Register (LFSR) based S-Box. As a result, a total of six AES ciphers with different S-box architectures are synthesized and implemented on FPGA platform. Considering both the hardware size (total Logic Elements (LE)) as well as the performance (throughput (Mbps)) the optimum AES cipher implementation is derived in this work. The presented implementation is proven lower in hardware area occupancy and higher in computational speed compared to the existing works.