Automatic approximation for 1-Dimensional Feedback-Loop Computations: a PID Benchmark

The analysis and optimization of computational precision is crucial when using approximation in hardware implementations of algorithms. Mainstream methods are based on either dynamic or static analysis of arithmetic errors, but only static analysis can guarantee the desired worst-case accuracy. In this paper we describe an automated approach to estimate the arithmetic binary representations and compare the computational sensitivities for 1-dimensional feedback-loop algorithms, enabling both customized floating-point and fixed-point approximation by affine arithmetic. Using typical benchmarks for iterative Proportional Integral Derivative (PID) control, an automated approach has been developed to obtain the appropriate approximation for both the exponent and mantissa of floating-point, and the integer and fraction parts of fixed-point signals. This reduces the circuit area and power consumption of an FPGA implementation. For the approximate PID controller implemented on a Xilinx FPGA platform, we were able to reduce area and power, as compared to standard uniform bit-widths, by 62% and 27% on average respectively.