ASIC Implementation Trade-Offs for High-Speed LMS and Block LMS Adaptive Filters

Mohd. Tasleem Khan; Oscar Gustafsson

doi:10.1109/MWSCAS54063.2022.9859296

ASIC Implementation Trade-Offs for High-Speed LMS and Block LMS Adaptive Filters

Mohd. Tasleem Khan, Oscar Gustafsson

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

1 Citation (Scopus)

Abstract

In this work, implementation trade-offs for ASICimplementation of least-mean-square (LMS) and block LMS (BLMS) adaptive filters are presented. We explore the design trade-offs by increasing the block size and/or relying on the synthesis tool for increased sample rate. For area, lower block size is advantageous as long as the synthesis tool can meet timing. Energy optimum is however found at a different point in design space. Simulation confirms that longer block sizes leads to lower MSE errors for identical step-size. Hence, the design-point should be decided based on weighted requirements for area, energy and MSE.

Original language	English
Title of host publication	65th IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)
Publisher	IEEE
ISBN (Electronic)	9781665402798
DOIs	https://doi.org/10.1109/MWSCAS54063.2022.9859296
Publication status	Published - 22 Aug 2022
Event	65th IEEE International Midwest Symposium on Circuits and Systems 2022 - Fukuoka, Japan Duration: 7 Aug 2022 → 10 Aug 2022

Conference

Conference	65th IEEE International Midwest Symposium on Circuits and Systems 2022
Abbreviated title	MWSCAS 2022
Country/Territory	Japan
City	Fukuoka
Period	7/08/22 → 10/08/22

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

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10.1109/MWSCAS54063.2022.9859296

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title = "ASIC Implementation Trade-Offs for High-Speed LMS and Block LMS Adaptive Filters",

abstract = "In this work, implementation trade-offs for ASICimplementation of least-mean-square (LMS) and block LMS (BLMS) adaptive filters are presented. We explore the design trade-offs by increasing the block size and/or relying on the synthesis tool for increased sample rate. For area, lower block size is advantageous as long as the synthesis tool can meet timing. Energy optimum is however found at a different point in design space. Simulation confirms that longer block sizes leads to lower MSE errors for identical step-size. Hence, the design-point should be decided based on weighted requirements for area, energy and MSE.",

author = "Khan, {Mohd. Tasleem} and Oscar Gustafsson",

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AU - Gustafsson, Oscar

PY - 2022/8/22

Y1 - 2022/8/22

N2 - In this work, implementation trade-offs for ASICimplementation of least-mean-square (LMS) and block LMS (BLMS) adaptive filters are presented. We explore the design trade-offs by increasing the block size and/or relying on the synthesis tool for increased sample rate. For area, lower block size is advantageous as long as the synthesis tool can meet timing. Energy optimum is however found at a different point in design space. Simulation confirms that longer block sizes leads to lower MSE errors for identical step-size. Hence, the design-point should be decided based on weighted requirements for area, energy and MSE.

AB - In this work, implementation trade-offs for ASICimplementation of least-mean-square (LMS) and block LMS (BLMS) adaptive filters are presented. We explore the design trade-offs by increasing the block size and/or relying on the synthesis tool for increased sample rate. For area, lower block size is advantageous as long as the synthesis tool can meet timing. Energy optimum is however found at a different point in design space. Simulation confirms that longer block sizes leads to lower MSE errors for identical step-size. Hence, the design-point should be decided based on weighted requirements for area, energy and MSE.

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DO - 10.1109/MWSCAS54063.2022.9859296

M3 - Conference contribution

AN - SCOPUS:85137508346

BT - 65th IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)

PB - IEEE

T2 - 65th IEEE International Midwest Symposium on Circuits and Systems 2022

Y2 - 7 August 2022 through 10 August 2022

ER -

ASIC Implementation Trade-Offs for High-Speed LMS and Block LMS Adaptive Filters

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