Applying a robust heteroscedastic probabilistic neural network to analog fault detection and classification

Zheng Rong Yang, Mark Zwolinski, Chris D. Chalk, Alan Christopher Williams

    Research output: Contribution to journalArticle

    49 Citations (Scopus)

    Abstract

    The problem of distinguishing and classifying the responses of analog integrated circuits containing catastrophic faults has aroused recent interest. The problem is made more difficult when parametric variations are taken into account. Hence, statistical methods and techniques such as neural networks have been employed to automate classification. The major drawback to such techniques has been the implicit assumption that the variances of the responses of faulty circuits have been the same as each other and the same as that of the fault-free circuit. This assumption can be shown to be false. Neural networks, moreover, have proved to be slow. This paper describes a new neural network structure that clusters responses assuming different means and variances. Sophisticated statistical techniques are employed to handle situations where the variance tends to zero, such as happens with a fault that causes a response to be stuck at a supply rail. Two example circuits are used to show that this technique is significantly more accurate than other classification methods. A set of responses can be classified in the order of 1 s.

    Original languageEnglish
    Pages (from-to)142-151
    Number of pages10
    JournalIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
    Volume19
    Issue number1
    DOIs
    Publication statusPublished - 2000

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