An improved parallel archutecture for MPEG-4 motion estimation in 3G mobile applications

Donglai Xu; Rui Gao; Hadj Batatia

doi:10.1109/ICASSP.2003.1202460

An improved parallel archutecture for MPEG-4 motion estimation in 3G mobile applications

Donglai Xu^*
, Rui Gao
, Hadj Batatia

^*Corresponding author for this work

School of Mathematical & Computer Sciences

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

2 Citations (Scopus)

Abstract

A high-parallel VLSI core architecture for MPEG-4 motion estimation is proposed in this paper. It possesses the characteristics of low memory bandwidth and low clock rate requirements, thus primarily aiming at 3G mobile applications. Based on a one-dimensional tree architecture, the architecture employs the dual-register/buffer technique to reduce the preload and alignment cycles. As an example, full-search block matching algorithm has been mapped onto this architecture using a 16-PE array that has the ability to calculate the motion vectors of QCIF video sequences in real time at 1 MHz clock rate and using 15.5 Mbytes/s memory bandwidth.

Original language	English
Title of host publication	2003 IEEE International Conference on Acoustics, Speech, and Signal Processing
Publisher	IEEE
Pages	689-692
Number of pages	4
ISBN (Print)	0780376633
DOIs	https://doi.org/10.1109/ICASSP.2003.1202460
Publication status	Published - 5 Jun 2003
Event	2003 IEEE International Conference on Accoustics, Speech, and Signal Processing - Hong Kong, Hong Kong Duration: 6 Apr 2003 → 10 Apr 2003

Conference

Conference	2003 IEEE International Conference on Accoustics, Speech, and Signal Processing
Country/Territory	Hong Kong
City	Hong Kong
Period	6/04/03 → 10/04/03

ASJC Scopus subject areas

Software
Signal Processing
Electrical and Electronic Engineering

Access to Document

10.1109/ICASSP.2003.1202460

Cite this

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title = "An improved parallel archutecture for MPEG-4 motion estimation in 3G mobile applications",

abstract = "A high-parallel VLSI core architecture for MPEG-4 motion estimation is proposed in this paper. It possesses the characteristics of low memory bandwidth and low clock rate requirements, thus primarily aiming at 3G mobile applications. Based on a one-dimensional tree architecture, the architecture employs the dual-register/buffer technique to reduce the preload and alignment cycles. As an example, full-search block matching algorithm has been mapped onto this architecture using a 16-PE array that has the ability to calculate the motion vectors of QCIF video sequences in real time at 1 MHz clock rate and using 15.5 Mbytes/s memory bandwidth.",

author = "Donglai Xu and Rui Gao and Hadj Batatia",

year = "2003",

month = jun,

day = "5",

doi = "10.1109/ICASSP.2003.1202460",

language = "English",

isbn = "0780376633",

pages = "689--692",

booktitle = "2003 IEEE International Conference on Acoustics, Speech, and Signal Processing",

publisher = "IEEE",

address = "United States",

note = "2003 IEEE International Conference on Accoustics, Speech, and Signal Processing ; Conference date: 06-04-2003 Through 10-04-2003",

}

Xu, D, Gao, R & Batatia, H 2003, An improved parallel archutecture for MPEG-4 motion estimation in 3G mobile applications. in 2003 IEEE International Conference on Acoustics, Speech, and Signal Processing. IEEE, pp. 689-692, 2003 IEEE International Conference on Accoustics, Speech, and Signal Processing, Hong Kong, Hong Kong, 6/04/03. https://doi.org/10.1109/ICASSP.2003.1202460

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AU - Xu, Donglai

AU - Gao, Rui

AU - Batatia, Hadj

PY - 2003/6/5

Y1 - 2003/6/5

N2 - A high-parallel VLSI core architecture for MPEG-4 motion estimation is proposed in this paper. It possesses the characteristics of low memory bandwidth and low clock rate requirements, thus primarily aiming at 3G mobile applications. Based on a one-dimensional tree architecture, the architecture employs the dual-register/buffer technique to reduce the preload and alignment cycles. As an example, full-search block matching algorithm has been mapped onto this architecture using a 16-PE array that has the ability to calculate the motion vectors of QCIF video sequences in real time at 1 MHz clock rate and using 15.5 Mbytes/s memory bandwidth.

AB - A high-parallel VLSI core architecture for MPEG-4 motion estimation is proposed in this paper. It possesses the characteristics of low memory bandwidth and low clock rate requirements, thus primarily aiming at 3G mobile applications. Based on a one-dimensional tree architecture, the architecture employs the dual-register/buffer technique to reduce the preload and alignment cycles. As an example, full-search block matching algorithm has been mapped onto this architecture using a 16-PE array that has the ability to calculate the motion vectors of QCIF video sequences in real time at 1 MHz clock rate and using 15.5 Mbytes/s memory bandwidth.

UR - https://www.scopus.com/pages/publications/0141565186

U2 - 10.1109/ICASSP.2003.1202460

DO - 10.1109/ICASSP.2003.1202460

M3 - Conference contribution

AN - SCOPUS:0141565186

SN - 0780376633

SP - 689

EP - 692

BT - 2003 IEEE International Conference on Acoustics, Speech, and Signal Processing

PB - IEEE

T2 - 2003 IEEE International Conference on Accoustics, Speech, and Signal Processing

Y2 - 6 April 2003 through 10 April 2003

ER -

An improved parallel archutecture for MPEG-4 motion estimation in 3G mobile applications

Abstract

Conference

ASJC Scopus subject areas

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